JPS5856424A - パタ−ン形成法 - Google Patents

パタ−ン形成法

Info

Publication number
JPS5856424A
JPS5856424A JP56155467A JP15546781A JPS5856424A JP S5856424 A JPS5856424 A JP S5856424A JP 56155467 A JP56155467 A JP 56155467A JP 15546781 A JP15546781 A JP 15546781A JP S5856424 A JPS5856424 A JP S5856424A
Authority
JP
Japan
Prior art keywords
layer
stencil
stencil layer
pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56155467A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0119257B2 (enExample
Inventor
Mineo Ueki
植木　峰雄
Yoshiaki Mimura
三村　義昭
Fumihiko Yanagawa
柳川　文彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56155467A priority Critical patent/JPS5856424A/ja
Publication of JPS5856424A publication Critical patent/JPS5856424A/ja
Publication of JPH0119257B2 publication Critical patent/JPH0119257B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P50/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor

Landscapes

  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP56155467A 1981-09-30 1981-09-30 パタ−ン形成法 Granted JPS5856424A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56155467A JPS5856424A (ja) 1981-09-30 1981-09-30 パタ−ン形成法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56155467A JPS5856424A (ja) 1981-09-30 1981-09-30 パタ−ン形成法

Publications (2)

Publication Number Publication Date
JPS5856424A true JPS5856424A (ja) 1983-04-04
JPH0119257B2 JPH0119257B2 (enExample) 1989-04-11

Family

ID=15606683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56155467A Granted JPS5856424A (ja) 1981-09-30 1981-09-30 パタ−ン形成法

Country Status (1)

Country Link
JP (1) JPS5856424A (enExample)

Also Published As

Publication number Publication date
JPH0119257B2 (enExample) 1989-04-11

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