JPS5856424A - パタ−ン形成法 - Google Patents

パタ−ン形成法

Info

Publication number
JPS5856424A
JPS5856424A JP15546781A JP15546781A JPS5856424A JP S5856424 A JPS5856424 A JP S5856424A JP 15546781 A JP15546781 A JP 15546781A JP 15546781 A JP15546781 A JP 15546781A JP S5856424 A JPS5856424 A JP S5856424A
Authority
JP
Japan
Prior art keywords
layer
stencil
stencil layer
substrate
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15546781A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0119257B2 (enrdf_load_html_response
Inventor
Mineo Ueki
植木　峰雄
Yoshiaki Mimura
三村　義昭
Fumihiko Yanagawa
柳川　文彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15546781A priority Critical patent/JPS5856424A/ja
Publication of JPS5856424A publication Critical patent/JPS5856424A/ja
Publication of JPH0119257B2 publication Critical patent/JPH0119257B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
JP15546781A 1981-09-30 1981-09-30 パタ−ン形成法 Granted JPS5856424A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15546781A JPS5856424A (ja) 1981-09-30 1981-09-30 パタ−ン形成法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15546781A JPS5856424A (ja) 1981-09-30 1981-09-30 パタ−ン形成法

Publications (2)

Publication Number Publication Date
JPS5856424A true JPS5856424A (ja) 1983-04-04
JPH0119257B2 JPH0119257B2 (enrdf_load_html_response) 1989-04-11

Family

ID=15606683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15546781A Granted JPS5856424A (ja) 1981-09-30 1981-09-30 パタ−ン形成法

Country Status (1)

Country Link
JP (1) JPS5856424A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPH0119257B2 (enrdf_load_html_response) 1989-04-11

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