JPS5842259A - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法

Info

Publication number
JPS5842259A
JPS5842259A JP56139479A JP13947981A JPS5842259A JP S5842259 A JPS5842259 A JP S5842259A JP 56139479 A JP56139479 A JP 56139479A JP 13947981 A JP13947981 A JP 13947981A JP S5842259 A JPS5842259 A JP S5842259A
Authority
JP
Japan
Prior art keywords
chip
metal frames
metal
wires
insulating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56139479A
Other languages
English (en)
Japanese (ja)
Other versions
JPH022289B2 (enFirst
Inventor
Nobuhiko Mizuo
水尾　允彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56139479A priority Critical patent/JPS5842259A/ja
Publication of JPS5842259A publication Critical patent/JPS5842259A/ja
Publication of JPH022289B2 publication Critical patent/JPH022289B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP56139479A 1981-09-04 1981-09-04 半導体パッケージの製造方法 Granted JPS5842259A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56139479A JPS5842259A (ja) 1981-09-04 1981-09-04 半導体パッケージの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56139479A JPS5842259A (ja) 1981-09-04 1981-09-04 半導体パッケージの製造方法

Publications (2)

Publication Number Publication Date
JPS5842259A true JPS5842259A (ja) 1983-03-11
JPH022289B2 JPH022289B2 (enFirst) 1990-01-17

Family

ID=15246203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56139479A Granted JPS5842259A (ja) 1981-09-04 1981-09-04 半導体パッケージの製造方法

Country Status (1)

Country Link
JP (1) JPS5842259A (enFirst)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106635A (ja) * 1985-11-01 1987-05-18 Mitsubishi Electric Corp 半導体装置
US5093282A (en) * 1988-04-13 1992-03-03 Kabushiki Kaisha Toshiba Method of making a semiconductor device having lead pins and a metal shell
JPH0489926U (enFirst) * 1990-02-14 1992-08-05

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638846A (en) * 1979-09-07 1981-04-14 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638846A (en) * 1979-09-07 1981-04-14 Fujitsu Ltd Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106635A (ja) * 1985-11-01 1987-05-18 Mitsubishi Electric Corp 半導体装置
US5093282A (en) * 1988-04-13 1992-03-03 Kabushiki Kaisha Toshiba Method of making a semiconductor device having lead pins and a metal shell
JPH0489926U (enFirst) * 1990-02-14 1992-08-05

Also Published As

Publication number Publication date
JPH022289B2 (enFirst) 1990-01-17

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