JPS58197862A - Hermetic package for semiconductor device - Google Patents

Hermetic package for semiconductor device

Info

Publication number
JPS58197862A
JPS58197862A JP8093282A JP8093282A JPS58197862A JP S58197862 A JPS58197862 A JP S58197862A JP 8093282 A JP8093282 A JP 8093282A JP 8093282 A JP8093282 A JP 8093282A JP S58197862 A JPS58197862 A JP S58197862A
Authority
JP
Japan
Prior art keywords
leads
lead frames
bent
semiconductor device
alternately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8093282A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yamamichi
山道　信行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8093282A priority Critical patent/JPS58197862A/en
Publication of JPS58197862A publication Critical patent/JPS58197862A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to reduce the capacity between leads greatly and utilize glass sealed packages in a wider range by a method wherein the intermediate parts of lead frames are bent up and down partially alternately so that the lead frames are not faced directly to each other. CONSTITUTION:Sealing glass 12 is adhered on a ceramic base 11, the lead frames 13 are fixed thereon, and a part of the adjacent leads is bent up and down alternately so that the side surfaces of the leads are not faced directly. The lead frames do not have all the leads on the same plane, but are bent up and down alternately for example at a part so that the adjacent leads do not oppose the side surfaces thereof. In this manner, since parts without opposition of leads to each other are obtained, the capacity between the leads reduces by that amount.

Description

【発明の詳細な説明】 本発明は半導体装置用気密容器にかかり、とくにリード
間容量の小さな半導体装置用ガラス封止容器に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an airtight container for a semiconductor device, and particularly to a glass sealed container for a semiconductor device with a small capacitance between leads.

従来の半導体装置用のガラス封止谷−に於いては、リー
ドフレームは、シールガラス面の則一平面内に配置され
る様にガラスの中に固着されていたＯ 仁の様にリードフレームが配ｔｉ１れている場合。In conventional glass sealing holes for semiconductor devices, the lead frame is fixed in the glass so that it is located within a plane of the sealing glass surface. If it is distributed.

隣接するリード間の容量が、大きくなり半導体素子によ
っては、規格ｔ′＃４良さないものがあったＯこの様な
不都合に対して、リードフレームの配置を変える事によ
ってこれを防止しようとしたものが本発明である。The capacitance between adjacent leads becomes large, and some semiconductor devices do not meet the standard t'#4. We tried to prevent this problem by changing the arrangement of the lead frame. is the present invention.

すなわち本発明は、リードフレームの一部中間部分を交
互に上下に折り曲げて、リードフレーム同志が、直接対
面しない様にしたものである。That is, in the present invention, a part of the middle portion of the lead frame is alternately bent up and down so that the lead frames do not directly face each other.

次に本発明を実施例に基づき詳細に説明する。Next, the present invention will be explained in detail based on examples.

第１図は、従来の半導体装置用ガラス封止容器を示して
いる。尚、第１図（５）の円１０の部分を拡大して示し
たのが第１図０である。FIG. 1 shows a conventional glass sealed container for semiconductor devices. Note that FIG. 10 shows an enlarged view of the circle 10 in FIG. 1(5).

セラミックペース１上に、封止ガラス２が付けられてい
て、その上にリードフレーム３が、同一平面内に固着さ
れている。この様なパッケージの場合隣り同志のリード
のｇａＩｍが互いに対向している為、そのリード間の容
量が大きなものとなる。A sealing glass 2 is attached onto the ceramic paste 1, and a lead frame 3 is fixed thereon in the same plane. In such a package, since the gaIm of adjacent leads face each other, the capacitance between the leads becomes large.

特にリード長の長いリード間はど大きなものとなるＯ この様な欠点をなくす為０本発明では次の様に改善した
。In particular, the distance between the leads with long lead lengths becomes large. In order to eliminate such drawbacks, the present invention has improved as follows.

第２図は１本発明の実施例による半導体装置用ガラス封
止容器を示している。FIG. 2 shows a glass sealed container for a semiconductor device according to an embodiment of the present invention.

セラずツクペース１１上に、封止ガラス１２が付けられ
ていて、その上にリードフレーム１３が。A sealing glass 12 is attached to the ceramic paste 11, and a lead frame 13 is placed on top of the sealing glass 12.

固着されていて＠９同志のリードの一部分が、交互に上
下に曲げられてｉて直接リードの側面が。A part of the lead of the @9 comrade that is fixed is bent up and down alternately so that the side of the lead is directly exposed.

対面しない様になっている０尚、第２ａｌｌ（ハ）は第
２図（５）の円２０の部分を拡大して示し危斜視図であ
るＯ 本発明によるリードフレームは、従来のリードフレーム
の様に同一平面に全てのリードが存在するのでろなくて
、隣同志のリードがその１ＩｌｉｌＩｉを対向させない
様に例えば互い違いに一部分を上下に折ル曲げであるも
のである・この様にすれば、互いのリードが対向してい
ない部分が出来るので。The lead frame according to the present invention is different from the conventional lead frame. Instead of having all the leads on the same plane, for example, adjacent leads should alternately bend some parts up and down so that their 1IliilIi do not face each other. If you do this, This creates a part where the leads are not facing each other.

リード間の容量がその分にけ減少する事になる。The capacitance between the leads will decrease accordingly.

以上本発明の実施例ｔｒＩＡｌｉＫ、より簡単に説明し
たが、この発明を利用すれば、従来のリード間容蓋を大
輪に減少出来より広範ｉｔ！ＩＫガラス封止容器が利用
出来るものである。The embodiment of the present invention, trIAliK, has been explained more simply above, but if this invention is used, the conventional lead space can be reduced to a large size, and it can be used more widely! An IK glass sealed container can be used.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のガラス封止容器を示す図、第２＠は本発
明による一実施例會示す因である。 尚、図において、１．１１・・・・・・セライックベー
ス、１．１２・・・・・・封止ガラス、１．１３・・・
・・・リードフレームである。 ＃Ｉ　図 りつ ｊ￥７２　図 ７２θFIG. 1 shows a conventional glass sealed container, and FIG. 2 shows an embodiment according to the present invention. In addition, in the figure, 1.11...Ceraic base, 1.12...Sealing glass, 1.13...
...It is a lead frame. #I diagram ￥72 figure 72θ

Claims (1)

【特許請求の範囲】[Claims] 封止ガラス面のリードフレームの一部が同一平面には無
い事ｔ−特徴とする半導体装置用気密容器。An airtight container for a semiconductor device, characterized in that a part of a lead frame on a sealing glass surface is not on the same plane.
JP8093282A 1982-05-14 1982-05-14 Hermetic package for semiconductor device Pending JPS58197862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8093282A JPS58197862A (en) 1982-05-14 1982-05-14 Hermetic package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8093282A JPS58197862A (en) 1982-05-14 1982-05-14 Hermetic package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS58197862A true JPS58197862A (en) 1983-11-17

Family

ID=13732213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8093282A Pending JPS58197862A (en) 1982-05-14 1982-05-14 Hermetic package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS58197862A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06283662A (en) * 1992-12-03 1994-10-07 Linear Technol Corp Lead frame capacitor and capacitive coupling type isolator circuit using it

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06283662A (en) * 1992-12-03 1994-10-07 Linear Technol Corp Lead frame capacitor and capacitive coupling type isolator circuit using it
EP0600488A3 (en) * 1992-12-03 1995-02-01 Linear Techn Inc Lead frame capacitor and capacitively-coupled isolator circuit using same.
US5444600A (en) * 1992-12-03 1995-08-22 Linear Technology Corporation Lead frame capacitor and capacitively-coupled isolator circuit using the same
US5589709A (en) * 1992-12-03 1996-12-31 Linear Technology Inc. Lead frame capacitor and capacitively-coupled isolator circuit using same
US5650357A (en) * 1992-12-03 1997-07-22 Linear Technology Corporation Process for manufacturing a lead frame capacitor and capacitively-coupled isolator circuit using same
US5926358A (en) * 1992-12-03 1999-07-20 Linear Technology Corporation Lead frame capacitor and capacitively-coupled isolator circuit using same
US5945728A (en) * 1992-12-03 1999-08-31 Linear Technology Corporation Lead frame capacitor and capacitively coupled isolator circuit

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