JPS61253838A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS61253838A
JPS61253838A JP9492885A JP9492885A JPS61253838A JP S61253838 A JPS61253838 A JP S61253838A JP 9492885 A JP9492885 A JP 9492885A JP 9492885 A JP9492885 A JP 9492885A JP S61253838 A JPS61253838 A JP S61253838A
Authority
JP
Japan
Prior art keywords
bonded
semiconductor chip
die
ceramic base
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9492885A
Other languages
Japanese (ja)
Inventor
Yoshitoku Kawahara
川原　良徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP9492885A priority Critical patent/JPS61253838A/en
Publication of JPS61253838A publication Critical patent/JPS61253838A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

PURPOSE:To improve the die-bondability by means of flattening the bonded surface low melting point glass by a method wherein the bonding part of ceramic base whereon a semiconductor chip is to be bonded is not provided with recessed part. CONSTITUTION:The surface of ceramic base 1 is made even not to provide it with recessed part as seen in conventional surface while a grazed low melting point glass 2 with even thickness is mounted on the surface and then a semiconductor chip 3 is die-bonded on almost the central part of the glass 2. Through these procedures, bonded part of die-bonded semiconductor chip 3 can be provided with the maximum bonding strength.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体チップをセラミックベースにダイボン
デインクしてパッケージングするパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package in which a semiconductor chip is die-bonded and inked onto a ceramic base.

〔従来の技術〕[Conventional technology]

第２図は従来の半導体装置用パッケージの斜視図である
。図において、１１は、半導体チップをダイボンディン
グするセラミックベースであシ、セラミックベース１１
のほぼ中央部には凹み４が設けられ、この凹み４の底部
に低融点ガラスをグレーズし、このグレーズ面に半導体
チップをダイボンディングで取付け、セラミックベース
１１の上面周辺ＫＩＪ−ドフレーム５を熱圧着で取付け
た構造となっている。FIG. 2 is a perspective view of a conventional package for a semiconductor device. In the figure, 11 is a ceramic base to which a semiconductor chip is die-bonded.
A recess 4 is provided approximately in the center of the recess 4, the bottom of the recess 4 is glazed with low melting point glass, a semiconductor chip is mounted on this glazed surface by die bonding, and the KIJ-deframe 5 around the upper surface of the ceramic base 11 is heated. The structure is attached by crimping.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の従来のパッケージは、半導体チップをダイポンチ
インクする固着部が凹み空間となっているので、第３図
のセラミックベースの断面図に示すように１凹部４の底
面のグレイズした低融点ガラス２が凸凹となル、ダイボ
ンディングした半導体チップ３の固着部が部分的になシ
、接着強度が不十分になるという欠点があった。In the above-mentioned conventional package, the fixing part where the semiconductor chip is die punched is a recessed space, so as shown in the cross-sectional view of the ceramic base in FIG. There were disadvantages in that the bonding surface became uneven, the fixed portion of the die-bonded semiconductor chip 3 was partially damaged, and the adhesive strength was insufficient.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置用パッケージは、セラミックベース
部に凹みを持たせず、半導体チップをダイボンディング
する固着面が、セラミックベース上面周辺のリードフレ
ーム取付面と同一平面上にあらしめている。In the semiconductor device package of the present invention, the ceramic base portion does not have a recess, and the fixing surface on which the semiconductor chip is die-bonded is on the same plane as the lead frame mounting surface around the top surface of the ceramic base.

〔実施例〕〔Example〕

つぎに本発明を実施例によ多説明する。 Next, the present invention will be explained in more detail with reference to examples.

第１−は本発明の一実施例に係るセラミックベースと、
ダイボンディングした半導体チップとを示す断面図であ
る。図において、セラミックベース１の上面には、第３
図の従来例のようには凹部が設けられて番らず、全面一
様な平面であシ、その平面上のグレイズした低融点ガラ
ス２も一様な厚さであシ、この平面のほぼ中央位置に半
導体チップ３がダイボンディングされている。The first is a ceramic base according to an embodiment of the present invention,
FIG. 3 is a cross-sectional view showing a die-bonded semiconductor chip. In the figure, the upper surface of the ceramic base 1 has a third
Unlike the conventional example shown in the figure, there are no recesses and the entire surface is a uniform plane, and the glazed low melting point glass 2 on that plane also has a uniform thickness. A semiconductor chip 3 is die-bonded to the center position.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に１本発明は、セラミックベース部に半
導体チップをダイボンディングする固着ｓＫ凹みを設け
ないことによシ、固着面の低融点ガラスが凸凹の無い平
担なものとなシ、グイボンティング性を向上させる効果
がある。As explained above, one aspect of the present invention is that by not providing a fixing sK recess for die bonding a semiconductor chip to a ceramic base part, the low melting point glass on the fixing surface can be made flat without any unevenness. It has the effect of improving bonding properties.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例に係るセラミックベースとダ
イボンディングした半導体チップの断面図、第２図は従
来の半導体装置用パッケージの斜視図、第３図は従来の
パッケージのセラミックベースと半導体チップの断面図
である。 １．１１・・・・・・セラミックベース、２・・・・・
・低融点ガラス、３・・・・・・半導体チップ、４・・
・川凹み、５・・・・・・リードフレーム。FIG. 1 is a cross-sectional view of a semiconductor chip die-bonded to a ceramic base according to an embodiment of the present invention, FIG. 2 is a perspective view of a conventional semiconductor device package, and FIG. 3 is a ceramic base and semiconductor chip of a conventional package. FIG. 3 is a cross-sectional view of the chip. 1.11...Ceramic base, 2...
・Low melting point glass, 3... Semiconductor chip, 4...
・River dent, 5...Lead frame.

Claims (1)

【特許請求の範囲】[Claims] 半導体チップを低融点ガラスによりダイボンディングす
るセラミックベースを有する半導体装置用パッケージに
おいて、前記半導体チップが固着される固着面のある前
記セラミックベース上面が、全面一様な平面とされてい
ることを特徴とする半導体装置用パッケージ。A package for a semiconductor device having a ceramic base in which a semiconductor chip is die-bonded with a low melting point glass, characterized in that the upper surface of the ceramic base, which has a fixing surface to which the semiconductor chip is fixed, is a flat surface that is uniform throughout. Packages for semiconductor devices.
JP9492885A 1985-05-02 1985-05-02 Package for semiconductor device Pending JPS61253838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9492885A JPS61253838A (en) 1985-05-02 1985-05-02 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9492885A JPS61253838A (en) 1985-05-02 1985-05-02 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS61253838A true JPS61253838A (en) 1986-11-11

Family

ID=14123630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9492885A Pending JPS61253838A (en) 1985-05-02 1985-05-02 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS61253838A (en)

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