JPS63276255A - Cerdip-type semiconductor device - Google Patents
Cerdip-type semiconductor deviceInfo
- Publication number
- JPS63276255A JPS63276255A JP62111915A JP11191587A JPS63276255A JP S63276255 A JPS63276255 A JP S63276255A JP 62111915 A JP62111915 A JP 62111915A JP 11191587 A JP11191587 A JP 11191587A JP S63276255 A JPS63276255 A JP S63276255A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- ceramic substrate
- lead frame
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000000919 ceramic Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000011521 glass Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、サーデイプ箆パッケージの半導体装置、特に
半導体素子の、リードフレームに対する関係位置が、高
精度に要求される半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in a deep dip package, and particularly to a semiconductor device in which the relative position of a semiconductor element with respect to a lead frame is required to be highly accurate.
従来のサーデイプ型パッケージの半導体装置の製造につ
いて、第３図を参照して説明する。The production of a conventional semiconductor device in a cer-deep package will be explained with reference to FIG.
セラミック基板３は、その周縁上にガラス（低融点ガラ
ス）２を介して、リードフレーム１が融着でれている。A lead frame 1 is fused onto the periphery of the ceramic substrate 3 with a glass (low melting point glass) 2 interposed therebetween.
このセラミック基板３の中央部上に、半導体素子４をダ
イポンディングした後、半導体素子４の電極パッド６と
、リードフレーム１の内部先端部（以下、内部リードと
いう）ｌｂとをワイヤボンディングにより金属細線５で
接続する。次に第４図に示すようにあらかじめガラスシ
ール嘔れたセラミックキャップ７をセラミック基板３と
加圧成形法にょシ封止する。After die-bonding the semiconductor element 4 onto the center of the ceramic substrate 3, the electrode pads 6 of the semiconductor element 4 and the inner tip (hereinafter referred to as an inner lead) lb of the lead frame 1 are bonded using thin metal wires by wire bonding. Connect with 5. Next, as shown in FIG. 4, the ceramic cap 7, which has been sealed with a glass seal in advance, is sealed with the ceramic substrate 3 by pressure molding.
上述した従来のサーディプ型半導体装置では、半導体素
子のセラミック基板への固定は、リードフレームの位置
とは無関係にセラミック基板の外形を利用して位置決め
されていた。一方、リニアセンサのように半導体素子の
セラミック基板への固定位置精度がセラミック基板よシ
もリードフレームを基準として、±５０μｍ以下を要求
されるものがあるが、従来法でのり−ドフレームと半導
体素子の相対位置は約±２００μｍとなるので上記要求
値を満足することができない欠点があった。In the conventional cerdip type semiconductor device described above, the semiconductor element is fixed to the ceramic substrate using the outer shape of the ceramic substrate, regardless of the position of the lead frame. On the other hand, there are products such as linear sensors that require the positional accuracy of the semiconductor element to be fixed to the ceramic substrate to be ±50 μm or less with respect to the lead frame as a reference. Since the relative position of the elements is approximately ±200 μm, there was a drawback that the above required value could not be satisfied.
本発明の目的は、上記の欠点を除去し、半導体素子のリ
ードフレームに対する相対位置の精度を高めることので
きる半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can eliminate the above-mentioned drawbacks and improve the accuracy of the relative position of a semiconductor element with respect to a lead frame.
本発明のサーデイプ型パッケージの半導体装置は、リー
ドフレームの内部リードのうち、１以上の内部リードが
、そ九よシ分岐し、セラミック基板上の所定の位置に配
置てれた位置指定リードを有し、半導体素子は前記位置
指定リードを基準としてマウントちれてなるものである
。In the semiconductor device of the third type package of the present invention, one or more of the internal leads of the lead frame has position designating leads that are branched from one side to the other and placed at predetermined positions on the ceramic substrate. However, the semiconductor element is mounted and recessed with reference to the position specifying lead.
こ〜で内部リードとは、リードフレームの内部先端部で
あって、パッケージ内に含まれる部分をいう。Here, the internal lead refers to the internal tip of the lead frame and is included within the package.
内部リードから分岐された位置指定リードの位置は半導
体素子をダイボンディングする際の基準であるから、半
導体素子は製品としてのリード位置に対し精確に位置づ
けられる。位置指定リードの個数、その配置位置、形状
等は、実施例に示すように適宜定められる。Since the position of the position specifying lead branched from the internal lead is a reference when die bonding the semiconductor element, the semiconductor element can be accurately positioned with respect to the lead position as a product. The number of position designating leads, their arrangement positions, shapes, etc. are appropriately determined as shown in the embodiments.
以下、本発明の実施例につき図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１実施例は、半導体素子にも位置表示マークを付し、
このマークと位置指定リードとの位置合わせを行なうも
のである。第１図の平面因に示すように、リードフレー
ム１は側辺の対向位置にある内部リード１１ 、１２
、１３ 、１４がそれぞれ分岐した位置指定リードｌｌ
ａ、１２ａ。In the first embodiment, a position indicating mark is also attached to the semiconductor element,
This mark is aligned with the position designation lead. As shown in the plan view of FIG. 1, the lead frame 1 has internal leads 11 and 12 located at opposite positions on the sides.
, 13 and 14 are branched position designation leads ll, respectively.
a, 12a.
１３ａ、１４ａｌもつ。半導体素子４は側辺の４個所に
位置マーク４ａをもつ。位置表示マーク４ａ、および位
置指定リード１１ ａ〜１４ ａの先端はともにくさび
形になっているので、両者の先端を合わすようにして、
半導体素子４′ｔ−セラミック基板３にダイボンディン
グして固定する。It has 13a and 14al. The semiconductor element 4 has position marks 4a at four locations on its sides. The tips of the position display mark 4a and the position designation leads 11a to 14a are both wedge-shaped, so align the tips of both.
Semiconductor element 4't--fixed to ceramic substrate 3 by die bonding.
リードフレーム１はセラミック基板３にあらかじめ固定
てれているから、リードフレームｌに対する半導体素子
の相対位置精度は捉来の±２００μｍから±５０μｍま
で高めることができる。ダイボンディング後、金属細線
５による、ワイヤボンデングをなし、セラミックキャッ
プを封止することによりサーブイブ型半導体装置が形成
される。Since the lead frame 1 is fixed in advance to the ceramic substrate 3, the relative positional accuracy of the semiconductor element with respect to the lead frame 1 can be increased from ±200 μm to ±50 μm. After die bonding, wire bonding is performed using thin metal wires 5 and the ceramic cap is sealed to form a serve-even type semiconductor device.
次に、第２実施例につき、第２図を参照して説明する。Next, a second embodiment will be described with reference to FIG. 2.
この例では、４隅にある内部リード１５〜１８がそれぞ
れ分岐した位置指定リード１５ ａ〜１８ ａを有し、
半導体素子４の側辺を図中の点線で示すように、縦・横
方向に合わせるようにしている。In this example, the internal leads 15 to 18 at the four corners each have branched position designation leads 15a to 18a,
The sides of the semiconductor element 4 are aligned vertically and horizontally as shown by dotted lines in the figure.
なお、この実施例では、位置指定リード１５ ａ〜１８
ａも、金属細線５によって、電極パッドに接続し、外
部のリード本数を増大させない利点もある。ただし、位
置指定リード１５ ａ〜１８ ａが接続される電極パッ
ドは分岐もとの内部リードが接続される電極パッドと同
一性質のものであることはいうまでもない。In addition, in this embodiment, the position designation leads 15a to 18
A also has the advantage of not increasing the number of external leads because it is connected to the electrode pad by the thin metal wire 5. However, it goes without saying that the electrode pads to which the position specifying leads 15a to 18a are connected have the same properties as the electrode pads to which the original internal leads are connected.
以上説明したように、本発明はサーブイブ型半導体装置
において、リードフレームの内部リードに分岐した位置
指定リードを、複数個設け、この位置指定リードを基準
として、半導体素子をセラミック基板にダイマウントす
ることにより、半導体装置の外部リードに対して、半導
体素子の位ｆ！ｔを精確に定めることができる。したが
って、すニアセンサのように、上記位置精度の要求が厳
しい半導体装置に対して好適でるる。As explained above, the present invention provides a serve-even type semiconductor device with a plurality of position specifying leads branched from the internal leads of a lead frame, and a semiconductor element is die-mounted on a ceramic substrate using the position specifying leads as a reference. Therefore, the position of the semiconductor element relative to the external lead of the semiconductor device is f! t can be determined accurately. Therefore, it is suitable for semiconductor devices such as sunar sensors that have strict requirements for positional accuracy.
第１図、第２図は本発明の実施例の平面図、第３図は従
来例のサーブイブ型半導体装置のセラミックキャップ封
止前の斜視図、第４図は従来例の封止後の断面図である
。
１・・・リードフレーム、２・・・カラス、３・・・セ
ラミック基板、４・・・半導体素子、４ａ・・・位置表
示マーク、
１１〜１８・・・内部リード、
１１ ａ〜１８ ａ・・・位置指定リード。1 and 2 are plan views of the embodiment of the present invention, FIG. 3 is a perspective view of a conventional serve-even type semiconductor device before sealing with a ceramic cap, and FIG. 4 is a cross-section of the conventional example after sealing. It is a diagram. DESCRIPTION OF SYMBOLS 1... Lead frame, 2... Crow, 3... Ceramic substrate, 4... Semiconductor element, 4a... Position display mark, 11-18... Internal lead, 11 a-18 a. ...Position specified lead.
Claims (1)
フレームの内部リードのうち、１以上の内部リードが、
それより分岐し、セラミック基板上の所定の位置に配置
された位置指定リードを有し、半導体素子は前記位置指
定リードを基準としてマウントされてなることを特徴と
するサーデイプ型半導体装置。In a semiconductor device of a third-deep package, one or more of the internal leads of the lead frame is
1. A ceramic substrate type semiconductor device comprising a position specifying lead branching from the ceramic substrate and arranged at a predetermined position on a ceramic substrate, and a semiconductor element being mounted with the position specifying lead as a reference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111915A JPH07107922B2 (en) | 1987-05-08 | 1987-05-08 | Semiconductor type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111915A JPH07107922B2 (en) | 1987-05-08 | 1987-05-08 | Semiconductor type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63276255A true JPS63276255A (en) | 1988-11-14 |
| JPH07107922B2 JPH07107922B2 (en) | 1995-11-15 |
Family
ID=14573305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111915A Expired - Lifetime JPH07107922B2 (en) | 1987-05-08 | 1987-05-08 | Semiconductor type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07107922B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4979016A (en) * | 1988-05-16 | 1990-12-18 | Dallas Semiconductor Corporation | Split lead package |
-
1987
- 1987-05-08 JP JP62111915A patent/JPH07107922B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4979016A (en) * | 1988-05-16 | 1990-12-18 | Dallas Semiconductor Corporation | Split lead package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07107922B2 (en) | 1995-11-15 |
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