KR970024033A - Semiconductor package with transparent window and manufacturing method thereof - Google Patents

Semiconductor package with transparent window and manufacturing method thereof Download PDF

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Publication number
KR970024033A
KR970024033A KR1019950036167A KR19950036167A KR970024033A KR 970024033 A KR970024033 A KR 970024033A KR 1019950036167 A KR1019950036167 A KR 1019950036167A KR 19950036167 A KR19950036167 A KR 19950036167A KR 970024033 A KR970024033 A KR 970024033A
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KR
South Korea
Prior art keywords
lead frame
transparent window
ceramic plate
adhesive
semiconductor package
Prior art date
Application number
KR1019950036167A
Other languages
Korean (ko)
Other versions
KR100201384B1 (en
Inventor
유중하
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950036167A priority Critical patent/KR100201384B1/en
Priority to JP8012759A priority patent/JP2813873B2/en
Priority to CN96109668A priority patent/CN1061174C/en
Publication of KR970024033A publication Critical patent/KR970024033A/en
Application granted granted Critical
Publication of KR100201384B1 publication Critical patent/KR100201384B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Abstract

본 발명은 투명창을 구비한 반도체 패키지 및 그 제조방법에 관한 것이다. 본 발명의 반도체 패키지는 반도체칩과; 반도체 칩을 수용하기 위한 세라믹 판과; 세라믹 판과 접착되며, 절곡 형성된 리드 프레임과; 리드 프레임의 상부에 설치된 투명창과; 세라믹판 및 투명창의 일측에 부착된 접착제로 구성된다. 아울러, 반도체 패키지 제조방법은 계단형태로 절곡된 세라믹판을 제공하는 단계와; 세라믹판의 상단부에 세라믹판 접착제를 제공하는 단계와; 리드 프레임을 상기 세라믹판 접착제의 상부에 위치시키는 단계와; 세라믹 판과 리드 프레임을 고온로에 통과시키는 단계와; 세라믹 판에 다이 접착제를 도포시키는 단계와; 다이 접착제상에 반도체 치을 부착시키는 단계와; 반도체 칩의 패드와 리드 프레임의 인너 리드를 와이어 본딩시키는 단계와; 투명창 접착제가 부착된 투명창을 리드 프레임상에 안착시키는 단계와; 리드 프레임과 투명창을 고온로에 통과시켜 부착시키는 단계와; 리드 프레임을 절단하는 단계로 구성된다. 이와같이 구성된 반도체 패키지 및 그 제조방법은 세라믹 윗판과 세라믹판 접착제를 사용하지 않으므로 재료비 절감 및 공정을 줄이는 잇점이 있다. 아울러, 리드 프레임과 패키지가 부착된 면을 모두 활용할 수 있으므로 부착면적이 넓게 되는 잇점이 있다.The present invention relates to a semiconductor package having a transparent window and a method of manufacturing the same. The semiconductor package of the present invention comprises a semiconductor chip; A ceramic plate for accommodating a semiconductor chip; A lead frame bonded to the ceramic plate and bent; A transparent window provided on an upper portion of the lead frame; It consists of an adhesive attached to one side of the ceramic plate and the transparent window. In addition, the semiconductor package manufacturing method comprises the steps of providing a ceramic plate bent in a step shape; Providing a ceramic plate adhesive on an upper end of the ceramic plate; Positioning a lead frame on top of the ceramic plate adhesive; Passing the ceramic plate and lead frame through a high temperature furnace; Applying a die adhesive to the ceramic plate; Attaching a semiconductor tooth on a die adhesive; Wire bonding the inner lead of the pad and the lead frame of the semiconductor chip; Placing a transparent window with a transparent window adhesive on the lead frame; Passing the lead frame and the transparent window through the high temperature furnace to attach the lead frame and the transparent window; Cutting the lead frame. The semiconductor package and its manufacturing method configured as described above do not use the ceramic upper plate and the ceramic plate adhesive, and thus, there is an advantage of reducing the material cost and the process. In addition, since both the lead frame and the surface attached to the package can be utilized, there is an advantage that the attachment area is wide.

Description

투명창을 구비한 반도체 패키지 및 그 제조방법Semiconductor package with transparent window and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 3도는 본 발명의 일실시예에 따른 반도체 패키지의 단면도.3 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Claims (5)

반도체 칩과; 상기 반도체 칩을 수용하기 위한 세라믹 판과; 상기 세라믹 판과 접착되며, 꺽쇠형태로 절곡형성된 리드 프레임과; 상기 리드 프레임의 상부에 설치된 투명창과; 상기 세라믹판 및 투명창의 일측에 부착된 접착제로 구성되는 것을 특징으로 하는 투명창을 구비한 반도체 패키지.A semiconductor chip; A ceramic plate for receiving the semiconductor chip; A lead frame bonded to the ceramic plate and bent in a bracket shape; A transparent window provided on an upper portion of the lead frame; The semiconductor package having a transparent window, characterized in that consisting of an adhesive attached to one side of the ceramic plate and the transparent window. 제 1항에 있어서, 상기 리드 프레임과 투명창은 접착을 용이하게 하기 위하여 동일한 폭으로 배설되는 것을 특징으로 하는 투명창을 구비한 반도체 패키지.The semiconductor package with a transparent window according to claim 1, wherein the lead frame and the transparent window are disposed in the same width to facilitate adhesion. 계단형태로 절곡된 세라믹판을 제공하는 단계와; 상기 세라믹판의 상단부에 세라믹판 접착제를 제공하는 단계와; 리드 프레임을 상기 세라믹판 접착제의 상부에 위치시키는 단계와; 상기 세라믹 판과 리드 프레임을 고온로에 통과시키는 단계와; 상기 세라믹 판에 다이 접착제를 도포시키는 단계와; 상기 다이 접착제상에 반도체 칩을 부착시키는 단계와; 상기 반도체 칩의 패드와 리드 프레임의 인너 리드를 와이어 본딩시키는 단계와; 투명창 접착제가 부착된 투명창을 리드 프레임상에 안착시키는 단계와; 상기 리드 프레임과 투명창을 고온로에 통과시켜 부착시키는 단계와; 상기 리드 프레임을 절단하는 단계로 구성되는 것을 특징으로 하는 투명창을 구비한 반도체 패키지의 제조방법.Providing a ceramic plate bent in a step shape; Providing a ceramic plate adhesive on an upper end of the ceramic plate; Positioning a lead frame on top of the ceramic plate adhesive; Passing the ceramic plate and lead frame through a high temperature furnace; Applying a die adhesive to the ceramic plate; Attaching a semiconductor chip on the die adhesive; Wire bonding a pad of the semiconductor chip and an inner lead of a lead frame; Placing a transparent window with a transparent window adhesive on the lead frame; Passing the lead frame and the transparent window through a high temperature furnace to attach the lead frame and the transparent window; A method of manufacturing a semiconductor package having a transparent window, characterized in that for cutting the lead frame. 제 3항에 있어서, 상기 리드 프레임과 투명창을 부착하는 단계에서, 리드 프레임이 절곡형성되어 있으므로 통기구멍으로 단계적으로 공기를 외부로 배출 제거시키면서 부착되는 것을 특징으로 하는 투명창을 구비한 반도체 패키지의 제조방법.The semiconductor package having a transparent window according to claim 3, wherein in the attaching of the lead frame and the transparent window, the lead frame is bent and attached to the vent hole while exhausting air to the outside step by step. Manufacturing method. 제 4항에 있어서, 상기 통기구멍은 투명창 접착제와 세라믹판 접착제의 폭을 조절함에 의해 그 크기를 조절할 수 있도록 형성되는 것을 특징으로 하는 투명창을 구비한 반도체 패키지의 제조방법.The method of claim 4, wherein the vent hole is formed to adjust its size by adjusting widths of the transparent window adhesive and the ceramic plate adhesive. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036167A 1995-10-19 1995-10-19 Semiconductor package having a transparency lid KR100201384B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950036167A KR100201384B1 (en) 1995-10-19 1995-10-19 Semiconductor package having a transparency lid
JP8012759A JP2813873B2 (en) 1995-10-19 1996-01-29 Semiconductor package having transparent window and method of manufacturing the same
CN96109668A CN1061174C (en) 1995-10-19 1996-09-06 Semiconductor packaging with transparent window and its producing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950036167A KR100201384B1 (en) 1995-10-19 1995-10-19 Semiconductor package having a transparency lid

Publications (2)

Publication Number Publication Date
KR970024033A true KR970024033A (en) 1997-05-30
KR100201384B1 KR100201384B1 (en) 1999-06-15

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Application Number Title Priority Date Filing Date
KR1019950036167A KR100201384B1 (en) 1995-10-19 1995-10-19 Semiconductor package having a transparency lid

Country Status (3)

Country Link
JP (1) JP2813873B2 (en)
KR (1) KR100201384B1 (en)
CN (1) CN1061174C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100373699B1 (en) * 2000-08-04 2003-02-26 에쓰에쓰아이 주식회사 Method of making an air tight cavity in an assembly package for semi-conductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3129275B2 (en) * 1998-02-27 2001-01-29 日本電気株式会社 Semiconductor device
EP2013905A1 (en) * 2006-04-28 2009-01-14 TELEFONAKTIEBOLAGET LM ERICSSON (publ) A microwave chip supporting structure
US9142426B2 (en) * 2011-06-20 2015-09-22 Cyntec Co., Ltd. Stack frame for electrical connections and the method to fabricate thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388157B1 (en) * 1989-03-15 1994-02-16 Ngk Insulators, Ltd. Ceramic lid for sealing semiconductor element and method of sealing a semiconductor element in a ceramic package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100373699B1 (en) * 2000-08-04 2003-02-26 에쓰에쓰아이 주식회사 Method of making an air tight cavity in an assembly package for semi-conductor device

Also Published As

Publication number Publication date
CN1061174C (en) 2001-01-24
CN1149765A (en) 1997-05-14
JP2813873B2 (en) 1998-10-22
KR100201384B1 (en) 1999-06-15
JPH09181096A (en) 1997-07-11

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