JPS63120431A - Semiconductor device for electric power - Google Patents

Semiconductor device for electric power

Info

Publication number
JPS63120431A
JPS63120431A JP61268207A JP26820786A JPS63120431A JP S63120431 A JPS63120431 A JP S63120431A JP 61268207 A JP61268207 A JP 61268207A JP 26820786 A JP26820786 A JP 26820786A JP S63120431 A JPS63120431 A JP S63120431A
Authority
JP
Japan
Prior art keywords
semiconductor element
heat generating
trapezoidal
directly below
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61268207A
Other languages
Japanese (ja)
Inventor
Yoshihiro Horie
堀江　義弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61268207A priority Critical patent/JPS63120431A/en
Publication of JPS63120431A publication Critical patent/JPS63120431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/83141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve both heat radiation and the accuracy in diebonding by a method wherein an element substrate is scooped out in trapezoidal form from the opposite side of the element surface on the part directly below the heat generating part of a semiconductor element, and on the other band, a trapezoidal projection is provided on a heat radiating tab. CONSTITUTION:The title semiconductor device for electric power is composed of a semiconductor element 1 having a trapezoidal recess on the opposite side of the surface of the element directly below the heat generating part 2, a beat radiating tab 4 whereon said semiconductor element 1 is mounted on the trapezoidal projection a metal fine wire 6 with which the electrode of the semiconductor element 1 and an external lead 5 are connected, and a resin-sealing body with which the semiconductor element 1 is enveloped. For example, the semiconductor element 1, which is trapezoidally scooped at the part directly below the heat generating source 2, is die-bonded through the intermediary of solder and the like, and between the electrode of the semiconductor element 1 and the external lead 5 is connected by a metal fine wire 6.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電力用半導体素子の熱放散を良好に、かつダイ
ボンディングの精度の向上に効果にある電力用半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power semiconductor device that is effective in dissipating heat from a power semiconductor element and improving die bonding accuracy.

〔従来の技術〕[Conventional technology]

第３図の断面図に示す従来の電力用半導体装置において
半導体素子は、素子表面の反対側に施こされた人Ｕ又は
Ａｇ系のメタル層と鉛系の半田層を介在して放熱用タブ
に接続されている。In the conventional power semiconductor device shown in the cross-sectional view of FIG. It is connected to the.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

最近の電力用半導体素子はよシ高電力化の要請によシ、
半導体素子サイズの大型化並びに、熱放散を良くするた
めの半導体素子厚の薄化の傾向にある。この一つの方策
として、従来、一般に使用されている素子全体の厚さ１
２０〜１６０μｍに対して、最近基板厚さを極端に５０
μｍ程度に薄くして残シを素子強度を保つためにＡｕ又
はＡｇ系のメタルで５０μｍ厚にする方策が使用されて
いるが、基板とＡｕ又はＡｇ系のメタル層の熱膨張率の
差によシ半導体素子にクラックが入シやずいという欠点
がある。Recent power semiconductor devices are becoming more and more popular due to the demand for higher power.
There is a trend of increasing the size of semiconductor devices and decreasing the thickness of semiconductor devices to improve heat dissipation. As one measure for this, conventionally, the thickness of the entire element commonly used is 1
Recently, the substrate thickness has been drastically increased from 20 to 160 μm.
In order to maintain the strength of the device, the thickness of the remaining layer is made to be 50 μm using Au or Ag metal. However, due to the difference in thermal expansion coefficient between the substrate and the Au or Ag metal layer, However, it has the disadvantage that it can cause cracks in the semiconductor device.

上述した従来の熱放散を良くするために、半導体素子全
体の厚さを薄くするのに対し、本発明は半導体素子の発
熱部属下の基板抵抗を低減するためその部分の基板を薄
くシ、かつ放熱用タブに対しては薄くなった基板との熱
放散を良くするため放熱用タブ表面に台形状の凹起を設
けるという独創的内容を有する。In contrast to the above-mentioned conventional method in which the thickness of the entire semiconductor element is made thinner in order to improve heat dissipation, the present invention reduces the substrate resistance under the heat generating part of the semiconductor element by thinning the substrate in that area and making it thinner. The heat dissipation tab has an original feature in that trapezoidal depressions are provided on the surface of the heat dissipation tab in order to improve heat dissipation with the thinned substrate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明では半導体素子の発熱部直下部分で素子表面と反
対側から素子基板を台形状にえぐシとり、−方、放熱用
タブには、前述のえぐり取られた半導体素子が放熱用タ
ブと熱放散よく接続される様に、台形状の凸起部を有し
ている。In the present invention, the element substrate is scooped out in a trapezoidal shape from the side opposite to the element surface directly below the heat generating part of the semiconductor element. It has a trapezoidal protrusion so that it can be connected with good radiation.

〔実施例〕〔Example〕

次に、本発明を実施例により説明する。 Next, the present invention will be explained by examples.

第１図は本発明の実施例１の封止樹脂を省略し７た平面
図と断面図である。図において約４５°の傾斜の台形状
を有した放熱用タブ４の上面に丁度、重なる様に、半田
等３を介して、発熱源２の直下で台形状にえぐられた半
導体素子１がダイボンディングされ、半導体素子１の電
極と外部リード５との間は金属細線６で接続されている
。FIG. 1 is a plan view and a cross-sectional view of Example 1 of the present invention, with the sealing resin omitted. In the figure, the semiconductor element 1 hollowed out into a trapezoidal shape directly under the heat generating source 2 is placed on the die through solder etc. 3 so as to overlap the upper surface of the heat dissipation tab 4 which has a trapezoidal shape with an inclination of approximately 45°. Bonding is performed, and the electrodes of the semiconductor element 1 and the external leads 5 are connected by thin metal wires 6.

第２図は本発明の実施例２の断面図である。FIG. 2 is a sectional view of Example 2 of the present invention.

半導体素子に複数個の発熱源２を大電力用半導体装置に
おいては、発熱源から、放熱用タブまでの厚さは台形状
の大きさを変えることにより、任意に送べるため、半導
体素子の熱分布を均一にすることが容易である。In a high-power semiconductor device in which a plurality of heat generating sources 2 are mounted on a semiconductor element, the thickness from the heat generating source to the heat dissipation tab can be adjusted arbitrarily by changing the size of the trapezoid. It is easy to make the heat distribution uniform.

〔発明の効果〕〔Effect of the invention〕

上述の通や、本発明は、半導体素子の発熱部直下の基板
厚を薄くすることが出来るため、熱放散が大巾に向上し
、かつ半導体素子の厚さは発熱部以外の周辺部で、従来
と変らないので半導体素子のダイボンディング時のクラ
ックが防止できる。As described above, the present invention can reduce the thickness of the substrate directly under the heat generating part of the semiconductor element, so heat dissipation is greatly improved, and the thickness of the semiconductor element is reduced in the peripheral area other than the heat generating part. Since it is no different from the conventional method, cracks can be prevented during die bonding of semiconductor elements.

又、台形状の放熱用タブにより、半導体素子と放熱用タ
ブとのダイボンディング位置精度も大巾に向上し、後工
程のダイボンディング工程の作業能率向上に良い効果を
与えることが出来る５、In addition, the trapezoidal heat dissipation tab greatly improves the precision of the die bonding position between the semiconductor element and the heat dissipation tab, which has a positive effect on improving work efficiency in the subsequent die bonding process5.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａｕ本発明の実施例１の封止樹脂を省略した平
面図、同図ω）は断面図で第２図は実施例２の封止樹脂
を省略した断面図である。第３図は従来の電力用半導体
装置の封止樹脂を省略した断面図である。 １・・・・・・半導体素子、２・・・・・・発熱源、３
・・・・・・半田、４・・・・・・放熱用タブ、５・・
・・・・外部リード、６・・・・・・金属細線、７・・
・・・・Ａ　ｕ　ｏ　ｒ　Ａ　ｇ系のメタル層。 一某　ｌ　閲FIG. 1 (au, a plan view of Example 1 of the present invention with the sealing resin omitted, ω in the same figure) is a cross-sectional view, and FIG. 2 is a cross-sectional view of Example 2 with the sealing resin omitted. FIG. 3 is a cross-sectional view of a conventional power semiconductor device with the sealing resin omitted. 1...Semiconductor element, 2...Heat generation source, 3
...Solder, 4...Tab for heat dissipation, 5...
...External lead, 6...Metal thin wire, 7...
...Au or Ag type metal layer. A certain person

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の発熱部直下に、素子表面の反対側から台形
状の凹起部を有する半導体素子と、この半導体素子が塔
載された台形状の凸起部を有する放熱用タブと、前記半
導体素子の電極と外部リード間を接続する金属細線と、
前記半導体素子を包覆する封止樹脂体とからなる電力用
半導体装置。A semiconductor element having a trapezoidal concave portion directly below the heat generating portion of the semiconductor element from the opposite side of the surface of the element, a heat dissipation tab having a trapezoidal convex portion on which the semiconductor element is mounted, and the semiconductor element. A thin metal wire connecting between the electrode and the external lead,
A power semiconductor device comprising a sealing resin body covering the semiconductor element.
JP61268207A 1986-11-10 1986-11-10 Semiconductor device for electric power Pending JPS63120431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61268207A JPS63120431A (en) 1986-11-10 1986-11-10 Semiconductor device for electric power

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61268207A JPS63120431A (en) 1986-11-10 1986-11-10 Semiconductor device for electric power

Publications (1)

Publication Number Publication Date
JPS63120431A true JPS63120431A (en) 1988-05-24

Family

ID=17455407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61268207A Pending JPS63120431A (en) 1986-11-10 1986-11-10 Semiconductor device for electric power

Country Status (1)

Country Link
JP (1) JPS63120431A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254732A (en) * 1989-03-28 1990-10-15 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
US5202288A (en) * 1990-06-01 1993-04-13 Robert Bosch Gmbh Method of manufacturing an electronic circuit component incorporating a heat sink
WO1994023454A1 (en) * 1993-03-31 1994-10-13 Siemens Components, Inc. A pedestal lead frame for supporting a semiconductor chip
US5693572A (en) * 1993-12-20 1997-12-02 Sgs-Thomson Microelectronics, Inc. Ball grid array integrated circuit package with high thermal conductivity
JP2009286092A (en) * 2008-06-02 2009-12-10 Nippon Steel Corp Equipment box

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254732A (en) * 1989-03-28 1990-10-15 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
US5202288A (en) * 1990-06-01 1993-04-13 Robert Bosch Gmbh Method of manufacturing an electronic circuit component incorporating a heat sink
US5345106A (en) * 1990-06-01 1994-09-06 Robert Bosch Gmbh Electronic circuit component with heat sink mounted on a lead frame
WO1994023454A1 (en) * 1993-03-31 1994-10-13 Siemens Components, Inc. A pedestal lead frame for supporting a semiconductor chip
US5506425A (en) * 1993-03-31 1996-04-09 Siemens Components, Inc. Semiconductor device and lead frame combination
US5693572A (en) * 1993-12-20 1997-12-02 Sgs-Thomson Microelectronics, Inc. Ball grid array integrated circuit package with high thermal conductivity
JP2009286092A (en) * 2008-06-02 2009-12-10 Nippon Steel Corp Equipment box

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