JPH02254732A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH02254732A
JPH02254732A JP1077010A JP7701089A JPH02254732A JP H02254732 A JPH02254732 A JP H02254732A JP 1077010 A JP1077010 A JP 1077010A JP 7701089 A JP7701089 A JP 7701089A JP H02254732 A JPH02254732 A JP H02254732A
Authority
JP
Japan
Prior art keywords
chip
island
semiconductor chip
striped
recessions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1077010A
Other languages
Japanese (ja)
Inventor
Keiichiro Kondo
近藤　敬一朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1077010A priority Critical patent/JPH02254732A/en
Publication of JPH02254732A publication Critical patent/JPH02254732A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the chip slippage from occurring by a method wherein recessions are provided on the rear surface of semiconductor chip while projections opposite to the recessions are provided on an island. CONSTITUTION:Striped recessions 1ax, 1ay intersecting crosswise with each other are formed on the rear surface (a surface opposite to another surface provided with electric elements) of a semiconductor chip 1. On the other hand, striped projections 2ax, 2ay also intersecting crosswise with each other are formed on the surface of an island 2. Then, the semiconductor chip 1 is mounted by engaging the recessions 1ax, 1ay thereof with the projections 2ax, 2ay of the island 2. Through these procedures, any erroneous bonding process due to the chip slippage is avoidable while any gas produced during the curing process can easily be breathed and the chip 1 can be prevented from peeling off.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に関し、特にチップマウント
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to chip mounts.

〔従来の技術〕[Conventional technology]

第３図に示す通り、従来は、半導体チップ１の裏面が平
坦でかつ半導体チップ１をマウントするアイランド２も
チップ搭載面が平坦なものを用いて、マウント材を使用
して、アイランド２に半導体チップ１をマウントした構
造を有していた。As shown in FIG. 3, conventionally, the back side of the semiconductor chip 1 is flat and the island 2 on which the semiconductor chip 1 is mounted also has a flat chip mounting surface, and a mounting material is used to attach the semiconductor to the island 2. It had a structure in which chip 1 was mounted.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体集積回路は、半導体チップの裏面
及びアイランドの平面がどちらも平坦なので、マウント
材のキュア中にマウント材から発生するガス等により、
半導体チップ自体が傾いて、ボンディングずれを生じな
り、チップサイズが大きくなると、ガスが抜けにくくな
り、半導体チップとアイランドの間にガスが留り、チッ
プはがれが生じ易いという欠点がある。In the conventional semiconductor integrated circuit described above, both the back surface of the semiconductor chip and the plane of the island are flat, so gas generated from the mounting material while the mounting material is curing may cause damage to the semiconductor integrated circuit.
The semiconductor chip itself is tilted, causing bonding misalignment, and as the chip size increases, it becomes difficult for gas to escape, and gas remains between the semiconductor chip and the island, making it easy to peel off the chip.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、半導体チップの電気素子を
設けた面と対向する裏面に辺から中央に向けて走行する
ストライプ状の凹（又は凸）部を設け、アイランドのチ
ップ搭載面に辺から内側に向けて走行するストライプ状
の凸（又は凹）部を前記半導体チップの凹（又は凸）部
に対応して設けたというものである。In the semiconductor integrated circuit of the present invention, a striped concave (or convex) portion running from the side toward the center is provided on the back surface of the semiconductor chip opposite to the surface on which the electric element is provided, and a striped concave (or convex) portion is provided on the chip mounting surface of the island from the side. Striped convex (or concave) portions running inward are provided corresponding to the concave (or convex) portions of the semiconductor chip.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明の一実施例の概略図である。FIG. 1 is a schematic diagram of one embodiment of the invention.

半導体チップ１は、裏面（電気素子を設けた面と対向す
る面）に、チップ中心から各辺の中央に向って、ストラ
イプ状凹部（溝）ｌａｘ、１ａ３／を十字形に交叉させ
て形成しておく。アイランド２の表面には、中心から各
辺の中央に向って、ストライプ状凸部２ａｘ、２ａｙを
十字形に交叉させて形成しておく、半導体チップ１の凹
部（溝）は、ウェーハからチップを分離する時と、同様
にダイシング技術を流用して、研削を行い、形成する。The semiconductor chip 1 has striped recesses (grooves) lax, 1a3/ formed in a cross shape on the back surface (the surface opposite to the surface on which the electric elements are provided) from the center of the chip toward the center of each side. I'll keep it. On the surface of the island 2, striped protrusions 2ax and 2ay are formed in a criss-cross pattern from the center to the center of each side. Grinding is performed and formed using the same dicing technique as when separating.

又、アイランド２の凸部は、リードフレーム状態でエツ
チングにより形成する。凹部の幅は１ｍｍ、深さは０．
１ｍｍ前後とし、凸部の幅及び深さは若干小さな値にし
ておく、このように、形成した半導体チップ１の凹部と
アイランド２の凸部を合せることによりマウントする。Further, the convex portion of the island 2 is formed by etching the lead frame. The width of the recess is 1 mm and the depth is 0.
The width and depth of the convex portion are set to be approximately 1 mm, and the width and depth of the convex portion are set to slightly small values.In this way, the concave portion of the formed semiconductor chip 1 and the convex portion of the island 2 are aligned to mount.

なお、第２図に示すように、十文字の交差部分を削除し
た形状にしてもよい、又、半導体チップ側に凸部を、ア
イランド側に凹部を設けてもよい。Incidentally, as shown in FIG. 2, the cross section may be omitted, or a convex portion may be provided on the semiconductor chip side and a concave portion may be provided on the island side.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体チップ裏面に凹（
又は凸）部を設け、それに対応してアイランドに凸（又
は、凹）部を設けることにより、チップずれを防止でき
るとともに、チップずれにより発生するボンディングミ
スも防止できる効果があり、また、マウント材のキュア
中に発生するが抜は易くなりチップはがれを防止できる
効果がある。また、半導体チップとアイランドに十文字
形の凹（又は凸）部を設けておくと、大きさが異なるチ
ップでも、容易に、アイランド中央にマウントさせる事
ができる効果もある。As explained above, the present invention provides a recess (
By providing a corresponding convex (or convex) part on the island, it is possible to prevent chip misalignment and also prevent bonding errors caused by chip misalignment. Although this occurs during curing, it is easier to remove and has the effect of preventing chip peeling. Further, by providing a cross-shaped concave (or convex) portion on the semiconductor chip and the island, there is an effect that even chips of different sizes can be easily mounted at the center of the island.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す概略図、第２図は一実
施例の変形を示す概略図、第３図は従来例を示す概略図
である。 １・・・半導体チップ、ｌａｘ、ｌａｙ・・・ストライ
プ状凹部、２・・・アイランド、２ａｘ、２ａｙ。 ２ｂｘ１．２ｂｘ２．２ｂｙｌ、２ｂｙ２−・・ストラ
イプ状凸部、３・・・吊りビン。FIG. 1 is a schematic diagram showing an embodiment of the present invention, FIG. 2 is a schematic diagram showing a modification of the embodiment, and FIG. 3 is a schematic diagram showing a conventional example. 1...Semiconductor chip, lax, lay...Striped recess, 2...Island, 2ax, 2ay. 2bx1.2bx2.2byl, 2by2-...stripe-shaped convex portion, 3...hanging bottle.

Claims (1)

【特許請求の範囲】[Claims] 半導体チップの電気素子を設けた面と対向する裏面に辺
から中央に向けて走行するストライプ状の凹（又は凸）
部を設け、アイランドのチップ搭載面に辺から内側に向
けて走行するストライプ状の凸（又は凹）部を前記半導
体チップの凹（又は凸）部に対応して設けたことを特徴
とする半導体集積回路。Striped depressions (or protrusions) running from the sides toward the center on the back surface of the semiconductor chip that faces the surface on which the electrical elements are provided.
A semiconductor device characterized in that a striped convex (or concave) portion running inward from the side is provided on the chip mounting surface of the island corresponding to the concave (or convex) portion of the semiconductor chip. integrated circuit.
JP1077010A 1989-03-28 1989-03-28 Semiconductor integrated circuit Pending JPH02254732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1077010A JPH02254732A (en) 1989-03-28 1989-03-28 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1077010A JPH02254732A (en) 1989-03-28 1989-03-28 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02254732A true JPH02254732A (en) 1990-10-15

Family

ID=13621787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1077010A Pending JPH02254732A (en) 1989-03-28 1989-03-28 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02254732A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6218722A (en) * 1985-07-18 1987-01-27 Toshiba Corp Semiconductor device
JPS63120431A (en) * 1986-11-10 1988-05-24 Nec Corp Semiconductor device for electric power

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6218722A (en) * 1985-07-18 1987-01-27 Toshiba Corp Semiconductor device
JPS63120431A (en) * 1986-11-10 1988-05-24 Nec Corp Semiconductor device for electric power

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