JPH0425154A - Ic chip - Google Patents
Ic chipInfo
- Publication number
- JPH0425154A JPH0425154A JP13063090A JP13063090A JPH0425154A JP H0425154 A JPH0425154 A JP H0425154A JP 13063090 A JP13063090 A JP 13063090A JP 13063090 A JP13063090 A JP 13063090A JP H0425154 A JPH0425154 A JP H0425154A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- corners
- cut
- mechanical stress
- induced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 3
- 230000001133 acceleration Effects 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、I C(Integrated C1rc
uit)チップの改良に関し、特に、チップに生じる機
械的な応力を低減できるようにしたものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to an IC (Integrated C1rc)
This invention relates to improvements to the chip, in particular to reducing the mechanical stress generated in the chip.
〔従来の技術]
ICチップは、−枚のウェハに形成された複数のチップ
を分割する工程(ダイシング)を経て製造されるが、歩
留りを上げ且つダイシングを簡易にするため、通常は方
形をしている。[Prior Art] IC chips are manufactured through a process (dicing) in which multiple chips formed on a single wafer are divided, but in order to increase yield and simplify dicing, IC chips are usually rectangular. ing.
しかしながら、ICチップを方形とすると、第3図に示
すように、ICチップ1に温度分布が生じた際にチップ
の角に機械的な応力Sが発生し、その応力SによりIC
チップ1に形成したアルミ配線やポリシリコン配線等に
クランクが生じて断線したり、或いはトランジスタのし
きい値電圧が変動したりして、集積回路の特性が劣化し
てしまうという不具合がある。However, if the IC chip is rectangular, as shown in FIG.
There is a problem in that the aluminum wiring, polysilicon wiring, etc. formed on the chip 1 may crack and break, or the threshold voltage of the transistor may fluctuate, resulting in deterioration of the characteristics of the integrated circuit.
このため、ICチップ1の角の部分には、集積回路の特
性に影響を与えるような配線や素子等を形成することが
できず、例えば第3図に示すように、配線2等は、大き
な応力Sが発生ずる領域を避けて配設されるから、IC
チップの使用可能な面積(有効面積)が減少してしまう
という未解決の課題がある。特に、ICチップ1の面積
が大きくなると、それに連れて機械的な応力Sが増大し
て、有効面積はさらに減少してしまう。Therefore, it is not possible to form wiring or elements that would affect the characteristics of the integrated circuit in the corner portions of the IC chip 1. For example, as shown in FIG. Since the IC is placed avoiding areas where stress S is generated,
There is an unresolved problem that the usable area (effective area) of the chip is reduced. In particular, as the area of the IC chip 1 increases, the mechanical stress S increases accordingly, further reducing the effective area.
この発明は、このような従来の技術が有する未解決の課
題に着目してなされたものであり、機械的な応力が低減
され、有効面積の増大が図られるICチップを提供する
ことを目的としている。This invention was made in view of the unresolved problems of the conventional technology, and aims to provide an IC chip that reduces mechanical stress and increases the effective area. There is.
」二記目的を達成するために、本発明のICヂップは、
チップの角を落とした。” In order to achieve the second objective, the IC zip of the present invention has the following features:
I dropped the corner of the chip.
本発明のICチップは、チップの角を落としているため
、チップの角に発生ずる機械的応力が分散される。Since the IC chip of the present invention has rounded corners, mechanical stress generated at the corners of the chip is dispersed.
〔実施例] 以下、この発明の実施例を図面に基づいて説明する。〔Example] Embodiments of the present invention will be described below based on the drawings.
第1図及び第2図は、本発明の一実施例を示す図であり
、第1図はICチップIの平面図、第2図はICチップ
1の角の部分の拡大平面図である。1 and 2 are diagrams showing an embodiment of the present invention. FIG. 1 is a plan view of an IC chip I, and FIG. 2 is an enlarged plan view of a corner portion of the IC chip 1. FIG.
即ち、第1図に示すように、長方形のICチップ1は、
その表面」二にトランジスタ等の素子やアルミ配線等か
らなる集積回路が形成されるとともに、その四つの角が
切り落とされている。That is, as shown in FIG. 1, the rectangular IC chip 1 is
An integrated circuit consisting of elements such as transistors and aluminum wiring is formed on its surface, and its four corners are cut off.
本実施例では、第2図に示すように、ICチップ1の角
を、ICチップ1の辺に対して約45度の角度で切り落
としている。つまり、ICチップ1の周囲には、約13
5度の角が八つ形成されていることになる。In this embodiment, as shown in FIG. 2, the corners of the IC chip 1 are cut off at an angle of approximately 45 degrees with respect to the sides of the IC chip 1. In other words, around IC chip 1 there are approximately 13
This means that eight 5 degree angles are formed.
そして、ICチップ1は、図示しないパッケージに実装
され、例えばワイヤンノεンディング等によって外部機
器とデータの送受信が可能となる。The IC chip 1 is mounted in a package (not shown), and is capable of transmitting and receiving data to and from an external device by, for example, wireless ε-ending.
ここで、ICチップ1は、例えば加速試験時等にはオー
ブン等によって加熱されるし、通常の使用時には集積回
路内の電気抵抗等によって発熱するから、その表面上に
温度分布が発生し、ICチップ1の角の部分に機械的な
応力Sが生しるが、本実施例のICチップ1ば、その角
を落としているため、発生する応力Sは分散され、角を
落とさない場合に比べて小さくて済む。Here, the IC chip 1 is heated by an oven or the like during an accelerated test, for example, and heat is generated by electrical resistance within the integrated circuit during normal use, so a temperature distribution occurs on the surface of the IC chip 1. Mechanical stress S is generated at the corners of the chip 1, but since the corners of the IC chip 1 of this embodiment are rounded, the generated stress S is dispersed, and the stress is lower than when the corners are not rounded. It's small enough.
従って、ICチップ1の有効面積が増大するから、例え
ば配線2やその他の素子等をICチップ1上の広い範囲
に配設することができる。Therefore, the effective area of the IC chip 1 increases, so that, for example, the wiring 2 and other elements can be disposed over a wide range on the IC chip 1.
なお、機械的な応力を小さくするには、ICチップ1を
円板状に形成するのが最適ではあるが、ICチップ1を
円板状にすると、歩留りが著しく低減してしまうし、ダ
イシングも困難になるという不具合が生してしまう。In order to reduce mechanical stress, it is optimal to form the IC chip 1 into a disk shape, but if the IC chip 1 is formed into a disk shape, the yield will be significantly reduced and dicing will be difficult. This will cause problems such as difficulty.
しかし、本実施例にあっては、素子や配線等の領域とし
て使用されていなかったICチップ10角を落とすだけ
で済むから、歩留りが低減してしまうこともないし、ダ
イシングが特に困難になることもない。However, in this embodiment, since it is only necessary to drop the 10 square parts of the IC chip that are not used as areas for elements, wiring, etc., the yield does not decrease and dicing does not become particularly difficult. Nor.
なお、上記実施例では、ICチップ1の角を、ICチッ
プ1の辺に対して45度の角度で切り落とした場合につ
いて説明したが、角の落とし方はこれに限定されるもの
ではなく、例えば、上記135度の角を切り落として更
に大きな角度の角を形成してもよいし、或いは、ICチ
ップ1の角を円弧等の曲線状に落としてもよい。In addition, in the above embodiment, the case where the corner of the IC chip 1 is cut off at an angle of 45 degrees with respect to the side of the IC chip 1 has been described, but the method of cutting off the corner is not limited to this, and for example, , the 135 degree corner may be cut off to form a corner with a larger angle, or the corner of the IC chip 1 may be cut into a curved shape such as an arc.
以上説明したように、本発明によれば、ICチップの角
を落々したので、ICチップに住じる機械的な応力が低
減され、ICチップの有効面積が増大するという効果が
ある。As described above, according to the present invention, since the corners of the IC chip are rounded, the mechanical stress in the IC chip is reduced, and the effective area of the IC chip is increased.
第1図は本発明の一実施例におけるICチップの平面図
、第2回はICチップの角の部分の拡大乎面閾、第3回
は従来のICチップの角の部分の拡大平面図である。
1・・・ICチップ、
2・・・配線、
S・・・応力Fig. 1 is a plan view of an IC chip according to an embodiment of the present invention, Fig. 2 is an enlarged plan view of a corner portion of the IC chip, and Fig. 3 is an enlarged plan view of a corner portion of a conventional IC chip. be. 1...IC chip, 2...wiring, S...stress
Claims (1)
プ。(1) An IC chip characterized by having the corners of the chip cut off.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13063090A JPH0425154A (en) | 1990-05-21 | 1990-05-21 | Ic chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13063090A JPH0425154A (en) | 1990-05-21 | 1990-05-21 | Ic chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0425154A true JPH0425154A (en) | 1992-01-28 |
Family
ID=15038843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13063090A Pending JPH0425154A (en) | 1990-05-21 | 1990-05-21 | Ic chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0425154A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6657282B2 (en) | 1998-02-27 | 2003-12-02 | Fujitsu Limited | Semiconductor device having a ball grid array and a fabrication process thereof |
WO2023083435A1 (en) * | 2021-11-09 | 2023-05-19 | Telefonaktiebolaget Lm Ericsson (Publ) | Assymetric antenna-in-package for use in multiple polarizations |
-
1990
- 1990-05-21 JP JP13063090A patent/JPH0425154A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6657282B2 (en) | 1998-02-27 | 2003-12-02 | Fujitsu Limited | Semiconductor device having a ball grid array and a fabrication process thereof |
US6784542B2 (en) | 1998-02-27 | 2004-08-31 | Fujitsu Limited | Semiconductor device having a ball grid array and a fabrication process thereof |
US6987054B2 (en) | 1998-02-27 | 2006-01-17 | Fujitsu Limited | Method of fabricating a semiconductor device having a groove formed in a resin layer |
US7064047B2 (en) | 1998-02-27 | 2006-06-20 | Fujitsu Limited | Semiconductor device having a ball grid array and a fabrication process thereof |
US7556985B2 (en) | 1998-02-27 | 2009-07-07 | Fujitsu Microelectronics Limited | Method of fabricating semiconductor device |
WO2023083435A1 (en) * | 2021-11-09 | 2023-05-19 | Telefonaktiebolaget Lm Ericsson (Publ) | Assymetric antenna-in-package for use in multiple polarizations |
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