JP2900452B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2900452B2 JP2900452B2 JP31621189A JP31621189A JP2900452B2 JP 2900452 B2 JP2900452 B2 JP 2900452B2 JP 31621189 A JP31621189 A JP 31621189A JP 31621189 A JP31621189 A JP 31621189A JP 2900452 B2 JP2900452 B2 JP 2900452B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- wiring
- stress
- breaking stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路の製造方法に係り、より詳
しくは、パッケージ材から半導体集積回路に加わる破壊
応力を吸収する技術に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a technique for absorbing a breaking stress applied to a semiconductor integrated circuit from a package material.
従来はパッケージ材（主として樹脂が使用されてい
る）から半導体集積回路に加わる破壊応力を低応力樹脂
を使用して減らすか、半導体集積回路の配線にスリット
を入れ応力を吸収していた。Conventionally, the destructive stress applied to the semiconductor integrated circuit from the package material (mainly made of resin) is reduced by using a low-stress resin, or a slit is formed in the wiring of the semiconductor integrated circuit to absorb the stress.
市場の半導体集積回路は、微細化、多層化、大型化
し、さらには、集積回路を収容するパッケージの大型化
がともない、半導体集積回路自身の変形及びパッケージ
材（封止樹脂）からの破壊応力が増加し、半導体集積回
路の保護膜にクラックが発生し配線材の腐食、配線材の
スライド、断線、及び素子特性の劣化が誘発され、半導
体集積回路の信頼性が損なわれるという課題があった。
さらには、半導体集積回路の配線にスリットを入れ応力
を吸収していたが配線材にスリットを入れる方法では、
スリットを入れた事により配線幅が狭くなり電流容量が
減ってしまうという課題があった。そこで本発明は、前
記課題を解決することにある。Semiconductor integrated circuits in the market are becoming finer, multi-layered, and larger, and the package containing the integrated circuit is becoming larger. As a result, deformation of the semiconductor integrated circuit itself and breaking stress from the package material (sealing resin) are reduced. As a result, cracks occur in the protective film of the semiconductor integrated circuit, causing corrosion of the wiring material, sliding and disconnection of the wiring material, and deterioration of element characteristics.
Furthermore, the slits were inserted in the wiring of the semiconductor integrated circuit to absorb the stress, but in the method of slitting the wiring material,
There is a problem in that the slit has a narrow wiring width and a reduced current capacity. Then, this invention is in solving the said subject.
本発明の半導体集積回路は、少なくとも２層以上の配
線工程により製造される半導体集積回路において、半導
体集積回路の外周とパッド開口部との間で、かつパッド
開口部とパッド開口部の間に対応する部分に半導体集積
回路の機能に関係のない破壊応力吸収用配線を配置した
ことを特徴とする。A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit manufactured by a wiring process of at least two layers, wherein the semiconductor integrated circuit is provided between the outer periphery of the semiconductor integrated circuit and the pad opening and between the pad openings. A wiring for absorbing a fracture stress irrelevant to the function of the semiconductor integrated circuit is disposed in a portion where the semiconductor integrated circuit functions.
以下に本発明の実施例を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図および第２図は、本発明を示す平面図である。
一般的に半導体集積回路を樹脂封止するパッケージ材か
ら発生する破壊応力14は、半導体集積回路の使用される
周辺温度環境の変化が大きいほど大きくなり、樹脂収縮
時の応力がチップの表面破壊強度を越えた時、保護膜27
にクラックが入ったり、配線材26が腐食したりする。周
辺温度環境の変化による半導体集積回路を樹脂封止する
パッケージ材から発生する破壊応力14は半導体集積回路
のチップサイズが大きいほど、さらには半導体集積回路
を収容するパッケージサイズが大きいほど大きくなる。
また、半導体集積回路を樹脂封止するパッケージ材から
発生する破壊応力14および半導体集積回路から発生する
熱によるストレス13は、半導体集積回路の周辺部に集中
し、より多くはコーナー部分に集中する事が経験的に知
られている。本発明は、半導体集積回路の外周部に配置
した破壊応力吸収用配線材11により、半導体集積回路の
内部で使用している配線材15に加わる半導体集積回路を
樹脂封止するパッケージ材から発生する破壊応力14およ
び半導体集積回路から発生する熱によるストレス13を吸
収し、半導体集積回路の破壊を防止することができる。
半導体集積回路のコーナー部に配置した破壊応力吸収用
配線材12の幅を大きく取ることにより、より吸収力の高
い破壊応力吸収用配線材12を得ることが出来る。1 and 2 are plan views showing the present invention.
In general, the breaking stress 14 generated from a package material for sealing a semiconductor integrated circuit with a resin increases as the change in the ambient temperature environment in which the semiconductor integrated circuit is used increases. Over the protection film 27
Cracks or the wiring member 26 is corroded. The breaking stress 14 generated from the package material for sealing the semiconductor integrated circuit with the resin due to a change in the ambient temperature environment increases as the chip size of the semiconductor integrated circuit increases and as the size of the package accommodating the semiconductor integrated circuit increases.
In addition, the breaking stress 14 generated from the package material that seals the semiconductor integrated circuit with resin and the thermal stress 13 generated from the semiconductor integrated circuit concentrate on the periphery of the semiconductor integrated circuit, and more often on the corners. Is known empirically. The present invention is generated from a package material for resin-sealing a semiconductor integrated circuit added to a wiring material 15 used inside a semiconductor integrated circuit by a wiring material 11 for breaking stress arranged at an outer peripheral portion of the semiconductor integrated circuit. The destructive stress 14 and the stress 13 due to heat generated from the semiconductor integrated circuit are absorbed, thereby preventing the destruction of the semiconductor integrated circuit.
By increasing the width of the breaking stress absorbing wiring member 12 arranged at the corner of the semiconductor integrated circuit, it is possible to obtain the breaking stress absorbing wiring member 12 having a higher absorbing power.
第２図は、本発明の破壊応力吸収用配線材の断面図を
示す図であり、21は半導体基板、22は絶縁膜、23は下層
の配線材、24は層間絶縁膜、25は上層の配線材、26は半
導体集積回路の内部で使用している配線材、27はチップ
保護膜である。FIG. 2 is a cross-sectional view of a breaking stress absorbing wiring member of the present invention, in which 21 is a semiconductor substrate, 22 is an insulating film, 23 is a lower wiring material, 24 is an interlayer insulating film, and 25 is an upper layer. Wiring material, 26 is a wiring material used inside the semiconductor integrated circuit, and 27 is a chip protection film.
本発明は、パッド開口部の周りに集中する半導体装置
自身及び外部からの熱によりパッケージ材から発生する
破壊応力を吸収することができるため、半導体装置の破
壊を防止できる。According to the present invention, the destructive stress generated from the package material due to heat from the semiconductor device itself concentrated around the pad opening and from the outside can be absorbed, so that destruction of the semiconductor device can be prevented.
更に、パッド開口部とパッド開口部との間に半導体集
積回路の機能に関係のない配線を配置するため、パッド
開口部の位置を目安に配線を配置すれが良いため配線が
容易にできる。Furthermore, since wiring that is not related to the function of the semiconductor integrated circuit is arranged between the pad openings, the wiring can be easily arranged with the position of the pad opening as a guide.
更には、新たな工程を増やすことなく、また配線材の
面積を増やすことなく簡単に半導体集積回路の機能に関
係のない配線を配置することができる半導体集積回路を
提供することができる。Further, it is possible to provide a semiconductor integrated circuit in which wiring irrelevant to the function of the semiconductor integrated circuit can be easily arranged without increasing new steps and without increasing the area of the wiring material.
第１図は、本発明の半導体装置の実施例を示す図であ
る。 第２図は、本発明の半導体装置のチップ外周部に設けた
破壊応力吸収用配線材の実施例を示す図である。 第３図は、従来の半導体装置のスリットを入れた配線材
を示す図である。 11……チップ外周部に設けた破壊応力吸収用配線材 12……チップコーナー部に設けた破壊応力吸収用配線材 13……半導体装置から発生する熱によるストレス 14……半導体装置を封止するパッケージ材から発生する
破壊応力 15……半導体集積回路の内部で使用している配線材 16……パッド開口部 21……半導体装置の基板 22……絶縁膜 23……下層の破壊応力吸収用配線材 24……層間絶縁膜 25……上層の破壊応力吸収用配線材 26……半導体集積回路の内部で使用している配線材 27……チップ保護膜 31……スリット 32……配線材FIG. 1 is a diagram showing an embodiment of a semiconductor device of the present invention. FIG. 2 is a view showing an embodiment of a wiring material for breaking stress provided on an outer peripheral portion of a chip of a semiconductor device of the present invention. FIG. 3 is a diagram showing a wiring member having slits of a conventional semiconductor device. 11: Wiring material for breaking stress provided on the outer periphery of the chip 12: Wiring material for absorbing breaking stress provided at the corner of the chip 13: Stress due to heat generated from the semiconductor device 14: Sealing the semiconductor device Breaking stress generated from package material 15 Wiring material used inside semiconductor integrated circuit 16 Pad opening 21 Substrate of semiconductor device 22 Insulating film 23 Lower wiring for absorbing breaking stress Material 24: Interlayer insulating film 25: Wiring material for breaking stress in the upper layer 26: Wiring material used inside the semiconductor integrated circuit 27: Chip protective film 31: Slit 32: Wiring material
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/3205 - 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/3205-21/3213 H01L 21/768
Claims (1)
される半導体集積回路において、半導体集積回路の外周
とパッド開口部との間で、かつパッド開口部とパッド開
口部の間に対応する部分に半導体集積回路の機能に関係
のない破壊応力吸収用配線を配置したことを特徴とする
半導体集積回路。In a semiconductor integrated circuit manufactured by a wiring process of at least two layers, a portion corresponding to a portion between an outer periphery of a semiconductor integrated circuit and a pad opening and a portion between pad openings. A semiconductor integrated circuit, wherein a wiring for breaking stress irrespective of the function of the semiconductor integrated circuit is arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31621189A JP2900452B2 (en) | 1989-12-05 | 1989-12-05 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31621189A JP2900452B2 (en) | 1989-12-05 | 1989-12-05 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03177026A JPH03177026A (en) | 1991-08-01 |
| JP2900452B2 true JP2900452B2 (en) | 1999-06-02 |
Family
ID=18074538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31621189A Expired - Lifetime JP2900452B2 (en) | 1989-12-05 | 1989-12-05 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2900452B2 (en) |
-
1989
- 1989-12-05 JP JP31621189A patent/JP2900452B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03177026A (en) | 1991-08-01 |
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