JPH083008Y2 - Bipolar integrated circuit device - Google Patents

Bipolar integrated circuit device

Info

Publication number
JPH083008Y2
JPH083008Y2 JP7562390U JP7562390U JPH083008Y2 JP H083008 Y2 JPH083008 Y2 JP H083008Y2 JP 7562390 U JP7562390 U JP 7562390U JP 7562390 U JP7562390 U JP 7562390U JP H083008 Y2 JPH083008 Y2 JP H083008Y2
Authority
JP
Japan
Prior art keywords
chip
region
integrated circuit
peripheral portion
bipolar integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7562390U
Other languages
Japanese (ja)
Other versions
JPH0440549U (en
Inventor
仁紀 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP7562390U priority Critical patent/JPH083008Y2/en
Publication of JPH0440549U publication Critical patent/JPH0440549U/ja
Application granted granted Critical
Publication of JPH083008Y2 publication Critical patent/JPH083008Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Bipolar Integrated Circuits (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、バイポーラ集積回路、特に、そのチップの
能動領域の部分に加わるせん断応力を軽減する構造に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a bipolar integrated circuit, and more particularly to a structure for reducing shear stress applied to an active area portion of a chip thereof.

〔従来の技術〕[Conventional technology]

第2図は従来のバイポーラ集積回路チップの一例の周
辺部の構造を示す。
FIG. 2 shows a structure of a peripheral portion of an example of a conventional bipolar integrated circuit chip.

図において1aはチップ周辺部の不活性領域、2は能動
領域、3は絶縁膜、4はAl配線(ボンディングパットを
含む)である。
In the figure, 1a is an inactive region around the chip, 2 is an active region, 3 is an insulating film, and 4 is an Al wiring (including a bonding pad).

図では通常表面層を形成する表面保護膜は省いてあ
る。
In the figure, the surface protective film that normally forms the surface layer is omitted.

従来、バイポーラ集積回路チップでは、第2図に示す
ように、チップ周辺部分1aは表面が内側の能動領域2部
より低くなる。
Conventionally, in the bipolar integrated circuit chip, as shown in FIG. 2, the surface of the chip peripheral portion 1a is lower than the surface of the active region 2 inside.

チップの周辺部分の不活性領域1aは、直接回路の電気
的特性に寄与する作用は小さく、特別な場合を除き、チ
ップ周辺の機械的ダメージがそのまま能動領域のダメー
ジにならないように緩衝領域として作用したり、また
は、組立中に生じる能動領域の不具合がチップ端(絶縁
膜でカバーされてない基板の露出部分)に直接達しない
ように緩衝域として作用してきた。
The inactive region 1a on the periphery of the chip has a small effect that directly contributes to the electrical characteristics of the circuit, and acts as a buffer region so that mechanical damage around the chip does not directly damage the active region except in special cases. Or acts as a buffer to prevent defects in the active area that occur during assembly from directly reaching the chip edge (the exposed portion of the substrate that is not covered by the insulating film).

〔考案が解決しようとする課題〕[Problems to be solved by the device]

従来の上記のような構造の集積回路チップでは、チッ
プ表面が開放されている間、すなわち、樹脂封止される
までは、設計された意図に沿った電気的特性を示し、ま
た、当然、機械的ダメージがかかることがない。しか
し、樹脂封止すると、チップ表面にせん断応力が発生
し、特に、チップ周辺部で、せん断応力が大きくなるの
で、電気的特性の変動、Al配線4、表面保護膜、絶縁膜
3等の劣化が生じるという問題があった。
In the conventional integrated circuit chip having the above-mentioned structure, while the surface of the chip is open, that is, until it is sealed with resin, it exhibits electrical characteristics in accordance with the designed intention, and of course, the mechanical characteristics There is no target damage. However, when resin sealing is performed, shear stress is generated on the surface of the chip, and particularly, the shear stress becomes large in the peripheral portion of the chip, so that fluctuations in electrical characteristics, deterioration of the Al wiring 4, the surface protective film, the insulating film 3, etc. There was a problem that.

本考案は上記の問題を解消するためになされたもの
で、チップの能動領域部分に加わるモールド樹脂による
せん断応力の小さいものを提供することを目的とする。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a device having a small shear stress due to the molding resin applied to the active region of the chip.

〔課題を解決するための手段〕[Means for solving the problem]

本考案のバイポーラ集積回路装置は、チップの周辺部
を除く全域を凹状にエッチングし、エッチングした領域
内に能動部分を形成することで、チップの周辺部に表面
が内側の能動領域表面より高い凸状の不活性領域を形成
したものである。
In the bipolar integrated circuit device of the present invention, the entire surface except the peripheral portion of the chip is etched in a concave shape, and the active portion is formed in the etched region, so that the surface of the peripheral portion of the chip is higher than that of the inner active region surface. The inactive region is formed.

〔作用〕[Action]

上記のように、チップの能動領域部分の表面がチップ
周辺の不活性領域部分の表面より低いと、チップ周辺の
凸状部分には従来構造のチップの場合と同程度のモール
ド樹脂によるせん断応力が加わるが、能動領域部分に
は、周辺部の凸状部分が壁となり、従来構造のチップの
場合より遥かに小さいせん断応力しか加わらなくなる。
As described above, when the surface of the active area portion of the chip is lower than the surface of the inactive area portion around the chip, the convex portion around the chip is subjected to the same shear stress due to the mold resin as in the case of the chip having the conventional structure. In addition, however, the active area portion has a peripheral convex portion as a wall, which applies a shear stress much smaller than that in the case of the chip having the conventional structure.

〔実施例〕〔Example〕

第1図は本考案の一実施例のチップの周辺部の構造を
示す。
FIG. 1 shows a structure of a peripheral portion of a chip according to an embodiment of the present invention.

図において2、3、4は第2図の同一符号と同一また
は相当する部分を示し、1は表面が能動領域部分2の表
面より高い凸状のチップ周辺部の不活性領域である。
In the figure, reference numerals 2, 3 and 4 denote the same or corresponding portions as the same reference numerals in FIG. 2, and 1 denotes a convex inactive region in the peripheral portion of the chip whose surface is higher than the surface of the active region portion 2.

図でも第2図と同様に表面層を形成する表面保護膜は
省いてある。
Also in the figure, the surface protective film forming the surface layer is omitted as in FIG.

チップ周辺部の不活性領域1が上記のような構造の場
合は、樹脂モールドの際、凸状部分1の作用により、チ
ップ表面の凸状部分1から内側の能動領域2部分にせん
断応力が殆んど波及しなくなり、該領域2部分に位置す
る個々の素子、Al配線4、表面保護膜、絶縁膜3のせん
断応力は軽減される。
When the inactive region 1 on the periphery of the chip has the above-described structure, during the resin molding, due to the action of the convex portion 1, almost no shear stress is exerted from the convex portion 1 on the chip surface to the inner active region 2 portion. It will no longer spread, and the shear stress of the individual elements, the Al wiring 4, the surface protective film, and the insulating film 3 located in the region 2 will be reduced.

したがって、これらの構成材は殆んど劣化しなくな
り、集積回路素子の性能劣化が軽減され、特性が安定
し、信頼性が向上する。
Therefore, these components are hardly deteriorated, the performance deterioration of the integrated circuit element is reduced, the characteristics are stabilized, and the reliability is improved.

上記構造のチップの製作は、チップの周辺部を除く中
央部全域を凹状にエッチングし、エッチングした領域内
に能動部分(集積回路)を形成することで、チップの周
辺部を表面が内側の能動領域表面より高い凸状に形成す
る。
The chip with the above structure is manufactured by etching the entire central portion of the chip except the peripheral portion in a concave shape, and forming an active portion (integrated circuit) in the etched area. It is formed in a convex shape higher than the surface of the region.

なお、凹状のエッチング深さは、該チップのAl配線4
の高低差の最大値以上であればよい。
The concave etching depth is the same as the Al wiring 4 of the chip.
It is sufficient if it is equal to or more than the maximum value of the height difference of.

〔考案の効果〕[Effect of device]

以上説明したように、本考案によれば、樹脂モールド
の際、チップ周辺部の凸状の壁により、樹脂によるせん
断応力の内側の能動領域への波及が抑制されるので、電
気的特性変動が抑えられ、Al配線、表面保護膜、絶縁膜
の劣化が軽減され、信頼性が向上するという効果があ
る。
As described above, according to the present invention, when the resin is molded, the convex wall at the periphery of the chip suppresses the propagation of the shear stress due to the resin to the inner active region, so that the variation in the electrical characteristics is suppressed. This is effective in suppressing deterioration of Al wiring, surface protection film, and insulating film, and improving reliability.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の一実施例のチップの周辺部の構造を示
す断面図、第2図は従来のバイポーラ集積回路チップの
一例の周辺部の構造を示す断面図である。 1……凸状のチップ周辺部の不活性領域、2……能動領
域、3……絶縁膜、4……Al配線 なお図中同一符号は同一または相当する部分を示す。
FIG. 1 is a sectional view showing the structure of the peripheral portion of a chip according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of the peripheral portion of an example of a conventional bipolar integrated circuit chip. 1 ... Inactive region around convex chip, 2 ... Active region, 3 ... Insulating film, 4 ... Al wiring The same reference numerals in the drawings indicate the same or corresponding portions.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】チップの周辺部を除く全域を凹状にエッチ
ングし、エッチングした領域内に能動部分を形成するこ
とで、チップの周辺部に表面が内側の能動領域表面より
高い凸状の不活性領域を形成し、チップの能動領域の部
分に加わるモールド樹脂によるせん断応力を軽減させた
ことを特徴とするバイポーラ集積回路装置。
1. A convex inactive surface having a higher surface in the peripheral portion of the chip than the surface of the inner active region by etching the entire region except the peripheral portion of the chip in a concave shape and forming an active portion in the etched region. A bipolar integrated circuit device characterized in that a region is formed to reduce the shear stress due to the molding resin applied to the active region of the chip.
JP7562390U 1990-07-18 1990-07-18 Bipolar integrated circuit device Expired - Fee Related JPH083008Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7562390U JPH083008Y2 (en) 1990-07-18 1990-07-18 Bipolar integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7562390U JPH083008Y2 (en) 1990-07-18 1990-07-18 Bipolar integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0440549U JPH0440549U (en) 1992-04-07
JPH083008Y2 true JPH083008Y2 (en) 1996-01-29

Family

ID=31616360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7562390U Expired - Fee Related JPH083008Y2 (en) 1990-07-18 1990-07-18 Bipolar integrated circuit device

Country Status (1)

Country Link
JP (1) JPH083008Y2 (en)

Also Published As

Publication number Publication date
JPH0440549U (en) 1992-04-07

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