JPH0750748B2 - Semiconductor device having protective film and manufacturing method thereof - Google Patents

Semiconductor device having protective film and manufacturing method thereof

Info

Publication number
JPH0750748B2
JPH0750748B2 JP1243317A JP24331789A JPH0750748B2 JP H0750748 B2 JPH0750748 B2 JP H0750748B2 JP 1243317 A JP1243317 A JP 1243317A JP 24331789 A JP24331789 A JP 24331789A JP H0750748 B2 JPH0750748 B2 JP H0750748B2
Authority
JP
Japan
Prior art keywords
protective film
circuit element
element region
semiconductor substrate
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1243317A
Other languages
Japanese (ja)
Other versions
JPH03108335A (en
Inventor
克人 加藤
陽一 蛭田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1243317A priority Critical patent/JPH0750748B2/en
Publication of JPH03108335A publication Critical patent/JPH03108335A/en
Publication of JPH0750748B2 publication Critical patent/JPH0750748B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は保護膜を有する半導体装置とその製造方法に係
り、特に半導体集積回路の回路素子の放熱性の改善のた
めに回路上への耐放射線性を有する保護膜の形成方法の
改良に関する。
The present invention relates to a semiconductor device having a protective film and a method for manufacturing the same, and more particularly to improving heat dissipation of a circuit element of a semiconductor integrated circuit. The present invention relates to improvement of a method for forming a protective film having radiation resistance on a circuit.

(従来の技術) 従来、半導体基板上に集積回路が形成された場合には、
放射線(アルファ線など)等の外部からの影響を避ける
ために、その集積回路の最上層に保護膜が形成されてい
る。
(Prior Art) Conventionally, when an integrated circuit is formed on a semiconductor substrate,
A protective film is formed on the uppermost layer of the integrated circuit in order to avoid external influences such as radiation (alpha rays).

第4図に半導体基板上に形成された前記保護膜を有する
集積回路の構成をあらわす断面図を示す。
FIG. 4 is a sectional view showing the structure of an integrated circuit having the protective film formed on a semiconductor substrate.

すなわち、第4図の半導体基板1上に形成された集積回
路は、論理回路素子領域2と記憶回路素子領域3とで構
成される。さらに、それぞれの領域上にある第2層に配
線用保護膜4が形成され、最上層には放射線用保護膜5
が形成されている。
That is, the integrated circuit formed on the semiconductor substrate 1 of FIG. 4 is composed of the logic circuit element region 2 and the memory circuit element region 3. Further, the wiring protection film 4 is formed on the second layer on each region, and the radiation protection film 5 is formed on the uppermost layer.
Are formed.

そして前記記憶回路素子領域3内の記憶回路素子Aが、
スタティック・ランダム・アクセス・メモリ(SRAM)構
造にされており、その上層に配線6が設けられて、これ
を保護するために絶縁物からなる配線用保護膜4が形成
されている。
The memory circuit element A in the memory circuit element region 3 is
It has a static random access memory (SRAM) structure, on which wiring 6 is provided, and a wiring protective film 4 made of an insulating material is formed to protect this.

前記記憶回路素子AはSRAM構造であるため、所定量の放
射線を浴びても動作にエラーを起こさない耐放射線性が
要求されている。従って、耐放射線性のための保護膜も
必要となり、第4図の記憶回路素子Aの保護膜には膜厚
50μm程度の放射線用保護膜5が形成されている。
Since the memory circuit element A has an SRAM structure, it is required to have radiation resistance that does not cause an error in its operation even when exposed to a predetermined amount of radiation. Therefore, a protective film for radiation resistance is also required, and the protective film of the memory circuit element A shown in FIG.
A radiation protective film 5 having a thickness of about 50 μm is formed.

同様に論理回路素子領域2は、論理回路素子Bの上に配
線6が設けられ、これを保護する絶縁物からなる配線用
保護膜4が形成されている。
Similarly, in the logic circuit element region 2, the wiring 6 is provided on the logic circuit element B, and the wiring protection film 4 made of an insulating material for protecting the wiring 6 is formed.

さらに前記記憶回路素子Aの前記耐放射線性のための保
護膜5の形成時に、前記保護膜5が前記配線用保護膜4
上にも形成されている。
Furthermore, when the protective film 5 for the radiation resistance of the memory circuit element A is formed, the protective film 5 serves as the wiring protective film 4.
It is also formed on the top.

(発明が解決しようとする課題) 前述したように、半導体基板1上に形成された論理回路
素子領域2および記憶回路素子領域3は、共に最上層に
耐放射線性のための保護膜5が形成されている。
(Problems to be Solved by the Invention) As described above, in the logic circuit element region 2 and the memory circuit element region 3 formed on the semiconductor substrate 1, the protective film 5 for radiation resistance is formed on the uppermost layer. Has been done.

ところが前記論理回路素子Bは、素子構造的に耐放射線
性が良いため、前述したような保護膜5を本来必要とし
ない。逆にこの保護膜5が厚膜であるため、回路素子の
動作によって発生する熱が放熱し難くなるという弊害が
出てくる。
However, since the logic circuit element B has good radiation resistance in terms of the element structure, the protective film 5 as described above is essentially unnecessary. On the contrary, since the protective film 5 is a thick film, the heat generated by the operation of the circuit element becomes difficult to dissipate.

つまり、論理回路素子だけで構成され、前述したような
保護膜5を形成されていない集積回路に比べると放熱し
難いために、回路素子の誤動作や熱による損傷が起こり
易くなる。
That is, since it is difficult to radiate heat as compared with an integrated circuit which is composed of only logic circuit elements and in which the protective film 5 is not formed as described above, malfunction of the circuit elements and damage due to heat are likely to occur.

そこで本発明は、同一半導体基板上に形成された集積回
路が論理回路素子領域と記憶回路素子領域とを合せ持つ
回路で、特に耐放射線性のための保護膜が必要とされる
集積回路において、その集積回路内の論理回路素子の信
頼性を向上することを目的とする。
Therefore, the present invention is a circuit in which an integrated circuit formed on the same semiconductor substrate has both a logic circuit element region and a memory circuit element region, particularly in an integrated circuit requiring a protective film for radiation resistance, The purpose is to improve the reliability of logic circuit elements in the integrated circuit.

[発明の構成] (課題を解決するための手段) 本発明は従来技術がもつ課題を解決するために、半導体
基板上に形成された論理回路素子および記憶回路素子か
らなる半導体集積回路内の記憶回路素子領域の最上層に
形成された耐放射線性を有する第1の保護膜と、前記第
1の保護膜および前記論理回路素子領域との上層に形成
され、前記第1の保護膜設よりも十分に薄い第2の保護
膜を具備する半導体装置もしくは、半導体基板上に形成
された論理回路素子および記憶回路素子からなる半導体
集積回路内の記憶回路素子領域の最上層に形成された耐
放射線性を有する第1の保護膜を具備することを特徴と
する半導体装置を用いる。
[Structure of the Invention] (Means for Solving the Problems) In order to solve the problems of the prior art, the present invention relates to storage in a semiconductor integrated circuit including a logic circuit element and a storage circuit element formed on a semiconductor substrate. A radiation-resistant first protective film formed on the uppermost layer of the circuit element region, and an upper layer of the first protective film and the logic circuit element region, which are formed above the first protective film. Radiation resistance formed in the uppermost layer of a semiconductor device having a sufficiently thin second protective film or a memory circuit element region in a semiconductor integrated circuit including a logic circuit element and a memory circuit element formed on a semiconductor substrate A semiconductor device including a first protective film having: is used.

そして、これらの半導体装置は、半導体基板の同一面上
に論理回路素子と記憶回路素子とを合せ持つ集積回路を
形成する工程と、前記集積回路の上層に絶縁物からなる
配線用保護膜を形成する工程と、前記配線用保護膜の上
層に放射線保護用の前記第1の保護膜を形成する工程
と、前記記憶回路素子領域上以外の前記第1の保護膜を
完全除去する工程と、少なくとも前記第1の保護膜の上
層に放射線保護用の十分に薄い前記第2の保護膜を形成
する工程とからなる製造方法によって製造する。
In these semiconductor devices, a step of forming an integrated circuit having both a logic circuit element and a memory circuit element on the same surface of a semiconductor substrate, and a wiring protective film made of an insulating material on an upper layer of the integrated circuit. At least, a step of forming the first protective film for radiation protection on an upper layer of the wiring protective film, a step of completely removing the first protective film other than on the memory circuit element region, It is manufactured by a manufacturing method including a step of forming the sufficiently thin second protective film for radiation protection on the upper layer of the first protective film.

もしくは、半導体基板の同一面上に論理回路素子と記憶
回路素子とを合せ持つ集積回路を形成する工程と、前記
集積回路の上層に絶縁物からなる配線用保護膜を形成す
る工程と、前記配線用保護膜の上層に放射線保護用の前
記第1の保護膜を形成する工程と、前記記憶回路素子領
域上以外の前記第1の保護膜を完全除去する工程とを具
備することを特徴とする半導体装置の製造方法を用いて
前述の課題を解決する。
Alternatively, a step of forming an integrated circuit having both a logic circuit element and a memory circuit element on the same surface of a semiconductor substrate, a step of forming a wiring protective film made of an insulating material on the upper layer of the integrated circuit, and the wiring And a step of completely removing the first protective film other than on the memory circuit element region, the method further comprising: The aforementioned problems are solved by using a method for manufacturing a semiconductor device.

(作用) 以上のような、製造方法および構造による耐放射線性の
ための保護膜の形成によって、放射性を向上し、もって
回路素子の誤動作や熱による損傷が起こり難くし、集積
回路の信頼性を向上することができる。
(Operation) By forming a protective film for radiation resistance by the manufacturing method and structure as described above, radiation is improved, and malfunction of circuit elements and damage due to heat are less likely to occur, and reliability of integrated circuits is improved. Can be improved.

(実施例) 以下、図面を参照して本発明の実施例につき詳細に説明
する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図(a)ないし(c)は本発明の第1の実施例とし
て、半導体基板上に形成された集積回路に設ける耐放射
線性(アルファ線など)のための保護膜の製造工程を示
すものである。
1 (a) to 1 (c) show, as a first embodiment of the present invention, a process of manufacturing a protective film for radiation resistance (alpha rays, etc.) provided in an integrated circuit formed on a semiconductor substrate. It is a thing.

すなわち、第1図(a)は半導体基板1上に周知の工程
によって、論理回路素子領域2とSRAM構造Cを持つ記憶
回路素子領域3からなる集積回路が形成され、第2層に
は双方の回路素子領域上の配線8を保護する絶縁物から
なる配線用保護膜9が形成される。さらに、最上層には
放射線用保護膜として保護膜10が形成されている。
That is, as shown in FIG. 1A, an integrated circuit composed of a logic circuit element region 2 and a memory circuit element region 3 having an SRAM structure C is formed on a semiconductor substrate 1 by a well-known process. A wiring protective film 9 made of an insulating material for protecting the wiring 8 on the circuit element region is formed. Furthermore, a protective film 10 is formed on the uppermost layer as a protective film for radiation.

この保護膜10はポリイミドを塗布装置等によって、膜厚
45μm程度に形成されている。
This protective film 10 is formed by coating polyimide with a coating device or the like.
It is formed to about 45 μm.

そして第1図(b)に示すように前記保護膜10上に写真
蝕刻法を用いてレジストパターンが設けられ、エッチン
グ等を用いて前記論理回路素子領域2上の部分とボンデ
ィングパッド等の電極部分(図示せず)の保護膜が除去
される。
Then, as shown in FIG. 1B, a resist pattern is provided on the protective film 10 by using a photolithography method, and a portion on the logic circuit element region 2 and an electrode portion such as a bonding pad are formed by etching or the like. The protective film (not shown) is removed.

さらに第1図(c)に示すように、同図(b)の保護膜
10が除去された半導体基板1に、再度保護膜11としてポ
リイミドを塗布装置等によって、膜厚5μm程度に形成
させる。この半導体基板1について、ボンディングパッ
ド等の電極部分等(図示せず)の保護膜11が写真蝕刻法
を用いて除去される。
Further, as shown in FIG. 1C, the protective film of FIG.
On the semiconductor substrate 1 from which 10 has been removed, polyimide is formed again as a protective film 11 to a film thickness of about 5 μm by a coating device or the like. On this semiconductor substrate 1, the protective film 11 such as an electrode portion (not shown) such as a bonding pad is removed by using a photo-etching method.

また第2図(a)および(b)に第2の実施例を示す。
すなわち、第2図(a)は、前述した第1図(a)と全
く同様にして半導体基板1上に、論理回路素子領域2と
記憶回路素子領域3からなる集積回路が形成され、第2
層には双方の回路素子領域上の配線12を保護する絶縁物
からなる配線用保護膜13が形成される。さらに、最上層
に放射線用保護膜としてポリイミドを膜厚45μm程度に
形成されている保護膜14がある。
A second embodiment is shown in FIGS. 2 (a) and 2 (b).
That is, in FIG. 2A, an integrated circuit including a logic circuit element region 2 and a storage circuit element region 3 is formed on the semiconductor substrate 1 in the same manner as in FIG. 1A described above.
A wiring protective film 13 made of an insulating material for protecting the wirings 12 on both circuit element regions is formed on the layer. Further, there is a protective film 14 formed of polyimide with a film thickness of about 45 μm as a radiation protective film on the uppermost layer.

そして第2図(b)に示すように、保護膜14が第2図
(b)と同様にエッチング等を用いて、前記論理回路素
子領域2上の部分やボンディングパッド等の接続用電極
部分(図示せず)の保護膜が除去される。
Then, as shown in FIG. 2 (b), the protective film 14 is formed by etching or the like as in FIG. 2 (b) by using a portion on the logic circuit element region 2 or a connecting electrode portion (bonding pad or the like). The protective film (not shown) is removed.

また第3図(a)ないし(c)にダイナミック・ランダ
ム・アクセス・メモリ(DRAM)構造を持つ記憶回路素子
を含む半導体集積回路に本発明を適用した場合の例とし
ての第3の実施例を示す。すなわち、第3図(a)は半
導体基板1上に周知の工程によって、論理回路素子領域
15とDRAM構造Dを持つ記憶回路素子領域16からなる集積
回路が形成され、第2層には双方の回路素子領域上の配
線17を保護する絶縁物からなる配線用保護膜18が形成さ
れる。さらに、最上層には放射線用保護膜として保護膜
19が形成されている。この保護膜19はポリイミドを塗布
装置等によって、膜厚45μm程度に形成されている。
A third embodiment as an example in which the present invention is applied to a semiconductor integrated circuit including a memory circuit element having a dynamic random access memory (DRAM) structure is shown in FIGS. 3 (a) to 3 (c). Show. That is, FIG. 3A shows a logic circuit element region formed on the semiconductor substrate 1 by a known process.
15 and a memory circuit element region 16 having a DRAM structure D are formed, and a wiring protection film 18 made of an insulating material for protecting the wiring 17 on both circuit element regions is formed on the second layer. . Furthermore, the topmost layer is a protective film as a protective film for radiation.
19 are formed. The protective film 19 is formed of polyimide with a film thickness of about 45 μm by a coating device or the like.

そして第3図(b)においては、前述した第1図(b)
の製造工程と同様にして前記保護膜19上に写真蝕刻法を
用いてレジストポターンが設けられ、ドライエッチング
等を用いて、前記論理回路素子領域15上の部分やボンデ
ィングパッド等の電極部分(図示せず)の保護膜が除去
される。
And in FIG. 3 (b), the above-mentioned FIG. 1 (b) is shown.
A resist pattern is formed on the protective film 19 by using a photo-etching method in the same manner as in the manufacturing process of, and dry etching or the like is used to form a portion on the logic circuit element region 15 or an electrode portion such as a bonding pad ( The protective film (not shown) is removed.

さらに第3図(c)においては、前述した第1図(c)
の製造工程と同様にして、第3図(b)の保護膜19が除
去された半導体基板1に、再度保護膜20としてポリイミ
ドを塗布装置等によって、膜厚5μm程度に形成させ
る。この半導体基板1はボンディングパッド等の電極部
分等(図示せず)の保護膜20が第3図(b)と同様にド
ライエッチング等を用いて除去される。
Further, in FIG. 3 (c), FIG.
In the same manner as in the manufacturing process of, the semiconductor substrate 1 from which the protective film 19 of FIG. 3B has been removed is again formed with a film thickness of about 5 μm as a protective film 20 of polyimide by a coating device or the like. In this semiconductor substrate 1, the protective film 20 such as an electrode portion (not shown) such as a bonding pad is removed by dry etching or the like as in FIG. 3B.

そして本発明の第1および第3の実施例にあって、それ
ぞれ記憶回路素子領域の上層に設けられた放射線用保護
膜は予測される放射線量から算出した形成膜厚20乃至50
μmになるように形成され、さらにそれぞれ論理回路素
子領域の上層に設けられた放射線用保護膜は放射線量の
考慮を要さないため、この膜厚が5乃至10μm程度に形
成されている。
In each of the first and third embodiments of the present invention, the radiation protective film provided on the upper layer of the memory circuit element region has a film thickness of 20 to 50 calculated from the predicted radiation dose.
The thickness of the protective film for radiation formed on the upper layer of the logic circuit element region does not require consideration of the radiation dose, so that the film thickness is about 5 to 10 μm.

さらに前記記憶回路素子においては、記憶容量が16Kバ
イト以上のDRAM構造の記憶回路素子であり、あるいは記
憶容量が8Kバイト以上のSRAM構造の記憶回路素子であ
る。
Further, the storage circuit element is a storage circuit element having a DRAM structure having a storage capacity of 16 Kbytes or more, or a storage circuit element having an SRAM structure having a storage capacity of 8 Kbytes or more.

また、本発明はこのような実施例に限定されるものでは
なく、他にも発明の要旨を逸脱しない範囲で種々の変形
や応用が可能であることは勿論である。
Further, the present invention is not limited to such embodiments, and it goes without saying that various modifications and applications can be made without departing from the scope of the invention.

[発明の効果] 本発明は、以上説明したような製造方法および構造によ
る耐放射線性のための保護膜の形成によって、論理回路
素子上の耐放射線性のための保護膜を薄く、あるいは除
去できるので回路素子の動作によって発生する熱が放熱
し易くなり、回路素子の誤動作や熱による損傷が起こり
難く、半導体集積回路の信頼性を向上することができ
る。
[Effect of the Invention] According to the present invention, the protection film for radiation resistance on the logic circuit element can be thinned or removed by forming the protection film for radiation resistance by the manufacturing method and the structure as described above. Therefore, the heat generated by the operation of the circuit element is easily dissipated, the malfunction of the circuit element and the damage due to the heat are less likely to occur, and the reliability of the semiconductor integrated circuit can be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)ないし(c)はそれぞれ本発明の第1の実
施例としての半導体基板上に形成される集積回路の構成
を製造工程順にあらわす断面図、第2図(a)および
(b)はそれぞれ本発明の第2の実施例としての半導体
基板上に形成される集積回路の構成を製造工程順にあら
わす断面図、第3図(a)ないし(c)はそれぞれ第3
の実施例としての半導体基板上に形成される集積回路の
構成を製造工程順にあらわす断面図、第4図は従来例と
しての半導体基板上に形成される集積回路の構成をあら
わす断面図。 2…論理回路素子領域、3…記憶回路素子領域、9…配
線用保護膜、10…第1の保護膜、11…第2の保護膜。
1 (a) to 1 (c) are sectional views showing the structure of an integrated circuit formed on a semiconductor substrate as a first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2 (a) and 2 (b). 3A) is a cross-sectional view showing the configuration of an integrated circuit formed on a semiconductor substrate as a second embodiment of the present invention in the order of manufacturing steps, and FIGS. 3A to 3C are respectively third views.
4 is a cross-sectional view showing the configuration of an integrated circuit formed on a semiconductor substrate as an example of the above, in the order of manufacturing steps, and FIG. 4 is a cross-sectional view showing the configuration of an integrated circuit formed on a semiconductor substrate as a conventional example. 2 ... Logic circuit element region, 3 ... Memory circuit element region, 9 ... Wiring protective film, 10 ... First protective film, 11 ... Second protective film.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】同一の半導体基板上に形成された論理回路
素子および記憶回路素子からなる回路で前記記憶回路素
子領域の最上層に耐放射線性を有する第1の保護膜を形
成し、その第1の保護膜および前記論理回路素子領域の
上層に該第1の保護膜よりも十分に薄い第2の保護膜を
形成することを特徴とする半導体装置。
1. A first protective film having radiation resistance is formed on the uppermost layer of the memory circuit element region in a circuit composed of a logic circuit element and a memory circuit element formed on the same semiconductor substrate, and the first protective film is formed. A semiconductor device, wherein a second protective film, which is sufficiently thinner than the first protective film, is formed on the first protective film and the upper layer of the logic circuit element region.
【請求項2】半導体基板の同一面上に論理回路素子およ
び記憶回路素子とからなる集積回路を形成する第1の工
程と、 前記第1の工程によって形成された前記集積回路の上層
に絶縁物からなる配線用保護膜を形成する第2の工程
と、 前記第2の工程によって形成された配線用保護膜の上層
に放射線保護用の前記第1の保護膜を形成する第3の工
程と、 前記第3の工程によって形成された記憶回路素子領域上
以外の前記第1の保護膜を完全除去する第4の工程と、 前記第4の工程によって形成された前記第1の保護膜及
び論理回路素子領域との上層に放射線保護用の十分に薄
い前記第2の保護膜を形成する工程とを具備することを
特徴とする請求項(1)記載の半導体装置の製造方法。
2. A first step of forming an integrated circuit including a logic circuit element and a memory circuit element on the same surface of a semiconductor substrate, and an insulator on an upper layer of the integrated circuit formed by the first step. And a third step of forming the first protective film for radiation protection on an upper layer of the wiring protective film formed by the second step, A fourth step of completely removing the first protective film other than on the memory circuit element region formed by the third step; and the first protective film and the logic circuit formed by the fourth step. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming the second protective film that is sufficiently thin for radiation protection on the element region and the upper layer.
JP1243317A 1989-09-21 1989-09-21 Semiconductor device having protective film and manufacturing method thereof Expired - Fee Related JPH0750748B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1243317A JPH0750748B2 (en) 1989-09-21 1989-09-21 Semiconductor device having protective film and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1243317A JPH0750748B2 (en) 1989-09-21 1989-09-21 Semiconductor device having protective film and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH03108335A JPH03108335A (en) 1991-05-08
JPH0750748B2 true JPH0750748B2 (en) 1995-05-31

Family

ID=17102039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1243317A Expired - Fee Related JPH0750748B2 (en) 1989-09-21 1989-09-21 Semiconductor device having protective film and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0750748B2 (en)

Also Published As

Publication number Publication date
JPH03108335A (en) 1991-05-08

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