JPH0498875A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To protect a semiconductor memory against malfunction caused by alpharays by a method wherein a memory cell is covered with material which contains lead or lead oxide. CONSTITUTION:A word line 13 serving as the gate electrode of a transistor 12 is formed on an Si substrate 11, and impurity diffusion layers 14a and 14b serving as the source and the drain region of the transistor 12 on both the sides of the word line 13 inside the Si substrate 11. The word line 13 and others are covered with an SiO2 film 15 which serves as an interlaminar insulating film, and contact holes 16a and 16b are provided to the SiO2 film 15 so as to reach to both the impurity diffusion layers 14a and 14b. A polycrystalline Si film 21 serving as a memory node is connected to the impurity diffusion layer 14 through the intermediary of the contact hole 16a, and the polycrystalline Si film 21 is covered with a dielectric film 22. The dielectric film 22 and the others are covered with a polycrystalline Si film 23 which serves as the plate electrode of a capacitive element 17, the polycrystalline Si film 23 is covered with a PbOX film 24 which serves as an interlaminar insulating film. The Pb0X film 24 is formed in lamination through spin coating or sputtering or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory that stores information in memory cells.

[Summary of the invention]

The present invention improves soft error resistance in the semiconductor memory described above by covering memory cells with a layer containing lead or lead oxide.

[Problem to be solved by the invention]

However, there is a limit to the removal of the α-ray source from the Al wiring.

Moreover, the resin used for packaging also contains an α-ray source, and since this resin is an organic substance, it is more difficult to remove the α-ray source from this resin than in the case of Al wiring. .

Therefore, conventional semiconductor memories do not have sufficiently high soft error resistance.

[Means to solve the problem]

In the semiconductor memory according to the invention, the memory cells 26 are covered with a layer 24.34 containing lead or lead oxide.

[Function] In the semiconductor memory according to the present invention, since the layer 24.34 containing lead or lead oxide has an α-ray blocking ability, the incidence of α-rays into the memory cell 26 is blocked by this layer 24.34. This reduces malfunctions caused by alpha rays.

[Example] Hereinafter, the first and second embodiments of the present invention will be described with reference to FIGS. 1 and 2.
This will be explained with reference to the figures.

FIG. 1 shows a first embodiment applied to a stacked capacitance type DRAM. In this first embodiment, a word line 13, which is the gate electrode of a transistor 12, is formed on a Si substrate 11, and impurity diffusion, which is the source/drain region of the transistor 12, is formed in the Si substrate 11 on both sides of the word line 13. Layers 14a and 14b are formed.

The word line 13 and the like are covered with a 5iOz film 15 which is an insulating film between the eyebrows, and contact holes 16a and 16b reaching the impurity diffusion layers 14a and 14b are formed in the shape of a SiO□ film 15.

A polycrystalline Si film 21, which is a storage node of the capacitive element 17, is connected to the impurity diffusion layer 14a via a contact hole 16a, and the polycrystalline Si film 21 is covered with a dielectric film 22.

The dielectric film 22 and the like are covered with a polycrystalline Si film 23 which is a plate electrode of the capacitive element 17, and the polycrystalline Si film 23 is covered with a pbo film 24 which is an interlayer insulating film. Pb0
The X film 24 is laminated by spin coating, sputtering, or the like.

Also, this is the focus line patterned on the Pb0X film 24! The film 25 is connected to the impurity diffusion layer 14b via the contact hole 16b.

That is, in this first embodiment, the memory cell 26 is composed of the transistor 12 and the capacitive element 17.

In the first embodiment as described above, the bit line is formed by the Al film 25, but the memory cell 26 is covered with the Pb0X film 24 except for the contact hole 16b and its vicinity. This P b Ox H24 has an ability to block α rays.

For this reason, A! α rays from an α ray source such as the film 25 are incident on the Si substrate 11 etc., and electrons of the generated electron-hole pairs are captured by the polycrystalline Si film 21, which is a memory note, and information is reversed. That rarely happens.

Therefore, this first embodiment has fewer malfunctions due to alpha rays,
High resistance to soft errors.

Moreover, since the PBO film 24 can be reflowed at a lower temperature than Al, there is less re-diffusion of the impurity diffusion layers 14a, 14b during reflow, and high integration is possible in this first embodiment.

FIG. 2 shows a second embodiment that is applicable to semiconductor chips such as SRAM. In this second embodiment, a bonding pad 32 made of Al is provided around the periphery of a semiconductor chip 31.

The surface of the semiconductor chip 31, except for the bonding pads 32, is covered with an overcoat film 33, and a PbOx film 34 is further laminated on the overcoat film 33.

In such a second embodiment, even if the semiconductor chip 31 is sealed with resin in the patterning process following the wire bonding process, the α rays from the α ray source in the resin (not shown) are exposed to PbO.
x film 34. Therefore, this second embodiment also has high soft error resistance.

Note that, as is clear from FIG. 2A, the pboX film 34 is made so that the pboX film 34 and the bonding pad 32 do not come into contact with each other.
4 is patterned, but if patterning is performed in this manner, a Pb film that is a conductive film may be used instead of the PBO film that is an insulating film and the film 34.

〔Effect of the invention〕

The semiconductor memory according to the present invention has high resistance to soft errors since there are few malfunctions caused by α rays.

[Brief explanation of drawings]

FIG. 1 is a side sectional view of the first embodiment of the present invention, FIG. 2A is a side sectional view taken along line A-A in FIG. 2B, and FIG. 2B is a side sectional view of the second embodiment. FIG. In addition, in the code|symbol used in the drawing, it is 24.34-.--.--.Pb0X film|membrane memory cell. Agent Masaru Tsuchiya

Claims (1)

[Claims] Semiconductor memory in which the memory cells are covered with a layer containing lead or lead oxide.