JPS6136709B2 - - Google Patents
Info
- Publication number
- JPS6136709B2 JPS6136709B2 JP54036877A JP3687779A JPS6136709B2 JP S6136709 B2 JPS6136709 B2 JP S6136709B2 JP 54036877 A JP54036877 A JP 54036877A JP 3687779 A JP3687779 A JP 3687779A JP S6136709 B2 JPS6136709 B2 JP S6136709B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- resin layer
- semiconductor chip
- ray
- cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005260 alpha ray Effects 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 21
- 239000010410 layer Substances 0.000 description 34
- 230000007257 malfunction Effects 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000005394 sealing glass Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052776 Thorium Inorganic materials 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/1617—Cavity coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にダイナミツクメモリ
等の半導体素子を封止して成る半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device formed by sealing a semiconductor element such as a dynamic memory.
一般に、半導体素子は通常セラミツク、ガラス
若しくはプラスチツク(樹脂)等から成る封止体
により封止される。これらの封止体(以下、パツ
ケージと称す。)のうちとくにセラミツクパツケ
ージにおけるセラミツク材料にはppm程度のウ
ラニウム(U)やトリウム(Th)等が含まれて
いる。これらの不純物は、例えば16th
proceedings of reliability physics(1978),p88
に述べられているように、α線を放出し、このα
線によつてメモリ素子が誤動作してしまうことが
知られている。このために、半導体素子の信頼性
が著しく低下する場合がある。 In general, semiconductor elements are usually sealed with a sealing body made of ceramic, glass, plastic (resin), or the like. Among these sealed bodies (hereinafter referred to as packages), the ceramic materials of ceramic packages in particular contain about ppm of uranium (U), thorium (Th), and the like. These impurities are e.g.
proceedings of reliability physics (1978), p88
As described in
It is known that wires can cause memory devices to malfunction. For this reason, the reliability of the semiconductor device may be significantly reduced.
U及びThの自然崩壊のエネルギー分布は4〜
9MeVであるがパツケージ材料中で発生したα線
はその材料表面に出るまでに分子との衝突でエネ
ルギーを失うのでパツケージから放射されるα線
のエネルギー分布は0〜9MeVとなる。 The energy distribution of spontaneous decay of U and Th is 4~
Although the α rays generated in the package material lose energy due to collisions with molecules before reaching the surface of the material, the energy distribution of the α rays emitted from the package is 0 to 9 MeV.
このα線がSiペレツト内に侵入すると電子を励
起し、少しづつエネルギーを失いながら走行す
る。従つて、物質中のα線の飛程は物質の密度に
反比例し、初期エネルギーに比例する。Si中では
3.6eVの電子を励起し5MeVのとき飛程は約25μ
mである。又、Si中で電子が励起されると、ホー
ルも発生することになり、電子−ホールのペアが
α線の軌跡に沿つて発生することになる。ここで
励起された電子数Neはα線エネルギーが5MeVと
すると、
Ne5MeV/8.6eV=1.4×106個
となる。これは0.22pグロンの電気量となる。以
後濃度勾配による拡散と共に再結合により消滅す
るが、この電荷がバイアスにより補捉され、ペレ
ツトのある境界条件の電荷量に比して無視できな
い値であつた時、誤動作するわけである。この誤
動作は素子の物理的性質をそこなわずに起るため
ソフト・エラー(Soft Error)と呼ばれている。 When this alpha ray enters the Si pellet, it excites electrons and travels while gradually losing energy. Therefore, the range of alpha rays in a substance is inversely proportional to the density of the substance and proportional to its initial energy. In Si
When exciting electrons at 3.6eV and 5MeV, the range is about 25μ
It is m. Further, when electrons are excited in Si, holes are also generated, and electron-hole pairs are generated along the trajectory of the α ray. The number of excited electrons Ne here is Ne5MeV/8.6eV=1.4×10 6 when the α-ray energy is 5MeV. This is an amount of electricity of 0.22 pgrons. Thereafter, the charge disappears due to diffusion and recombination due to the concentration gradient, but this charge is captured by the bias, and when it reaches a value that cannot be ignored compared to the amount of charge under a certain boundary condition of the pellet, a malfunction occurs. This malfunction is called a soft error because it occurs without damaging the physical properties of the device.
このような誤動作を防止するため、パツケージ
を封止する前に半導体チシプの活性領域表面にα
線遮蔽用のポリイミド系レジン層を被着すること
すでに提案されている。しかしながら、この場
合、十分なα線遮蔽効果を得るためには、80μm
以上の厚さに均一にレジンコーテイングを施す必
要があり、現状の塗布技術ではこのようなコーテ
イングを施すのは容易でない欠点があつた。 To prevent such malfunctions, α is applied to the surface of the active region of the semiconductor chip before sealing the package.
It has already been proposed to apply a polyimide resin layer for radiation shielding. However, in this case, in order to obtain a sufficient α-ray shielding effect, it is necessary to
It is necessary to uniformly apply a resin coating to the above thickness, and the current coating technology has the drawback that it is not easy to apply such a coating.
本発明の目的は、このような欠点を伴うことな
く活性領域でのα線による誤動作を防止した半導
体装置を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which malfunctions caused by alpha rays in an active region are prevented without having such drawbacks.
本発明による半導体装置は、半導体チツプの活
性領域面にα線遮蔽用レジンを被着し、かつパツ
ケージのキヤツプの凹部内面にα線遮蔽体を設け
ることにより半導体チツプ上に被着すべきα線遮
蔽用レジン層の厚さを薄くしてその形成工程の簡
略化を図つたもので、以下、添付図面に示す実施
例について詳述する。 In the semiconductor device according to the present invention, α-ray shielding resin is applied to the surface of the active region of the semiconductor chip, and an α-ray shielding member is provided on the inner surface of the recess of the cap of the package. The thickness of the shielding resin layer is reduced to simplify the formation process, and the embodiment shown in the accompanying drawings will be described in detail below.
第1図は、本発明の一実施例による半導体装置
を示すもので、セラミツク製の絶縁性ベース10
の上面周辺部には低融点ガラス層11により多数
のリード線12が接着されると共に、ベース10
の上面中央の凹部底面にはAuフオイル又はAuメ
タライズ層などからなる接着層13を介して半導
体チツプ14が固着されている。この半導体チツ
プ14は、例えばシリコンからなり、後述するメ
モリセル等を含むα線照射により誤動作しやすい
活性領域が通常約4〜5μmの深さにわたつて形
成されている。そして、半導体チツプ14上の多
数の電極は多数のボンデイングワイヤ15により
対応するリード12にそれぞれ電気的に接続され
る。 FIG. 1 shows a semiconductor device according to an embodiment of the present invention, in which an insulating base 10 made of ceramic
A large number of lead wires 12 are bonded to the periphery of the upper surface by a low melting point glass layer 11, and the base 10
A semiconductor chip 14 is fixed to the bottom of the recess at the center of the upper surface via an adhesive layer 13 made of Au foil or an Au metallized layer. This semiconductor chip 14 is made of, for example, silicon, and has an active region, which is likely to malfunction when irradiated with alpha rays, and which includes a memory cell, etc. (to be described later), usually having a depth of about 4 to 5 .mu.m. A large number of electrodes on the semiconductor chip 14 are electrically connected to corresponding leads 12 by a large number of bonding wires 15, respectively.
ワイヤボンデイングが終了した半導体チツプ1
4には、その表面の活性領域をおおうように、例
えばポリイミド・イソインドロ・キナゾリンデイ
オンのようなポリイミド系レジンからなるα線遮
蔽用レジン層16が被着される。このレジン層1
6の厚さは、30〜50μmでよい。 Semiconductor chip 1 after wire bonding
An α-ray shielding resin layer 16 made of a polyimide-based resin such as polyimide-isoindolo-quinazolindeion is deposited on the substrate 4 so as to cover the active region on its surface. This resin layer 1
6 may have a thickness of 30 to 50 μm.
一方、セラミツク製の絶縁性キヤツプ17は一
方の主表面に凹部17aを有し、この凹部17a
を半導体チツプ14に対向させるようにしてベー
ス10に重ね合わせるものである。キヤツプ17
のベース10との対向接合面には予め低融点ガラ
ス層18が被着すると共に、キヤツプ17の凹部
17aにはその内面全面をおおうように好ましく
はフアイブ・ナイン以上の高純度Alからなるα
線遮蔽体20が予め低融点ガラス層又は金属ろう
などの接着層19により固着されており、ベース
10にキヤツプ17を重ね合わせた後、封止用ガ
ラス層18の融点まで加熱し、冷却することによ
りベース10とキヤツプ17とが相互に接着され
る。 On the other hand, the insulating cap 17 made of ceramic has a recess 17a on one main surface.
is placed on the base 10 so as to face the semiconductor chip 14. cap 17
A low melting point glass layer 18 is preliminarily applied to the joint surface facing the base 10 of the cap 17, and a glass layer 18 made of high purity Al, preferably five nines or higher, is applied to the concave portion 17a of the cap 17 so as to cover the entire inner surface of the concave portion 17a.
The wire shielding body 20 is fixed in advance with an adhesive layer 19 such as a low-melting glass layer or a metal solder, and after the cap 17 is superimposed on the base 10, it is heated to the melting point of the sealing glass layer 18 and then cooled. The base 10 and cap 17 are bonded to each other.
ここで、α線遮蔽体20の材料としては、高純
度Alに限らず、高純度Si等を用いることができる
他、前述のレジン層16と同様のα線遮蔽能力の
あるレジンを用いることができる。Al,Si等の導
電材料をα線遮蔽体20として用いる場合には、
適当な酸化処理によりその表面を絶縁性にしてお
くのが、ボンデイングワイヤ15の短絡を防止す
る観点から好ましい。また、α線遮蔽体20の厚
さは、α線遮蔽効果に関係するものであり厚いほ
ど好ましいが、前述のレジン層16の厚さとの関
連で適当な厚さが決定される。一例として、レジ
ン層16を30〜50μmにした場合は最低50μm以
上任意の厚さのAl板を用いればよい。なお、凹
部17aの内面全周をおおうようにα線遮蔽体2
0を設けるのが最も好ましいが、凹部17aの内
面をどの程度の広さにわたつてα線遮蔽するかも
前述のレジン層16の厚さとの関連で適宜決定さ
れうるものである。 Here, the material of the α-ray shielding body 20 is not limited to high-purity Al, high-purity Si, etc. can be used, and a resin having the same α-ray shielding ability as the resin layer 16 described above can also be used. can. When using a conductive material such as Al or Si as the α-ray shield 20,
It is preferable to make the surface insulating through appropriate oxidation treatment from the viewpoint of preventing short circuits of the bonding wire 15. Further, the thickness of the α-ray shielding member 20 is related to the α-ray shielding effect and is preferably thicker, but an appropriate thickness is determined in relation to the thickness of the resin layer 16 described above. As an example, when the resin layer 16 is set to 30 to 50 μm, an Al plate having an arbitrary thickness of at least 50 μm may be used. Note that the α-ray shield 2 is placed so as to cover the entire inner circumference of the recess 17a.
Although it is most preferable to provide 0, the extent to which the inner surface of the recess 17a is shielded from α rays can be determined as appropriate in relation to the thickness of the resin layer 16 described above.
上記構成において、α線はベース10及びキヤ
ツプ17のセラミツクスと、封止ガラス層11,
18のガラスとから放射されるが、このうち、ベ
ース10から放射されるα線は半導体チツプ14
が150〜500μmの厚さを有するためチツプ表面の
活性領域に到達するまでにはその誤動作を生じさ
せえない程度に弱められているので殆ど問題にな
らない。そこで、問題となるのは、キヤツプ17
及び封止ガラス層11,18からのα線である
が、キヤツプ17からのα線はα線遮蔽体20及
びレジン層16で十分弱められると共に、封止ガ
ラス層11,18からのα線もチツプ14に対す
る入射角が比較的大きいものはα線遮蔽体20及
びレジン層16により十分弱められる。そして、
封止ガラス層11,18から放射されたα線のう
ち、α線遮蔽体20を経由しないようにチツプ1
4の側方から活性領域に入射するα線は、入射角
が浅くてレジン層16を通過する距離が長くなり
レジン層16によるα線減衰作用とにより殆んど
問題とならない。 In the above configuration, the α rays are transmitted to the ceramics of the base 10 and the cap 17, the sealing glass layer 11,
Among them, alpha rays emitted from the base 10 are emitted from the semiconductor chip 14.
Since it has a thickness of 150 to 500 μm, by the time it reaches the active region on the chip surface, it has been weakened to the extent that it will not cause any malfunction, so it poses little problem. Therefore, the problem is that cap 17
The alpha rays from the cap 17 are sufficiently weakened by the alpha ray shield 20 and the resin layer 16, and the alpha rays from the sealing glass layers 11 and 18 are also weakened. Those having a relatively large angle of incidence on the chip 14 are sufficiently weakened by the α-ray shield 20 and the resin layer 16. and,
The chip 1 is designed to prevent alpha rays emitted from the sealing glass layers 11 and 18 from passing through the alpha ray shielding body 20.
The α rays entering the active region from the sides of the active region have a shallow angle of incidence, have a long distance to pass through the resin layer 16, and are hardly a problem due to the α ray attenuating effect of the resin layer 16.
従つて、上記した本発明の半導体装置によれ
ば、α線遮蔽体20とα線遮蔽用レジン層16と
の協働作用により、活性領域に入射するα線量を
十分低下させ、活性領域に生じうる誤動作を末然
に防止することができるものである。その上、α
線遮蔽体20を設けたことによりチツプ14上に
被着すべきα線遮蔽用レジン層16の厚さを製造
上処理容易な程度にまで薄くすることができるの
で、製造工程の簡略化並びに製造歩留の向上を図
ることができる付随的効果も得られるものであ
る。なおα線遮蔽体20として用いる安価なAl
などの金属材は一般に有機レジン材にくらべて、
精製度が上がりにくいが、α線源を微量含んでも
ある限度以下ならばレジン層16の遮蔽効果で問
題にならないので、純度にそれ程神経質にならな
くてよい点も組合せの利点である。 Therefore, according to the above-described semiconductor device of the present invention, the α-ray shielding body 20 and the α-ray shielding resin layer 16 work together to sufficiently reduce the amount of α-rays incident on the active region, thereby reducing the amount of α-rays generated in the active region. This makes it possible to prevent malfunctions that may occur. Besides, α
By providing the radiation shielding body 20, the thickness of the α-ray shielding resin layer 16 to be deposited on the chip 14 can be reduced to a level that is easy to process in manufacturing, which simplifies the manufacturing process and facilitates manufacturing. Ancillary effects that can improve yield can also be obtained. In addition, inexpensive Al used as the α-ray shield 20
Generally speaking, metal materials such as
Although it is difficult to increase the degree of purification, the shielding effect of the resin layer 16 does not pose a problem even if a small amount of α-ray source is included, as long as it is below a certain limit, so an advantage of the combination is that there is no need to be too concerned about purity.
ところで、本発明の適用対象となる半導体装置
は、前述したようにα線照射により誤動作するこ
とのある活性領域が形成された半導体チツプを有
するものであるが、次にその具体例をいくつか説
明する。 By the way, as mentioned above, the semiconductor device to which the present invention is applied has a semiconductor chip in which an active region is formed that may malfunction due to alpha ray irradiation.Next, some specific examples will be explained. do.
第2図は、MOS型ダイナミツクRAM(ランダ
ム・アクセス・メモリ)のメモリセル構造を示す
もので、その等価回路は第3図に示されている。
20はP型シリコン基板で、その表面には厚いフ
イールドSiO2膜21が形成されると共に、この
SiO2膜21の開口部内には薄いSiO2膜21Aが
形成されている。22はN+型拡散領域、23は
第1の低抵抗ポリシリコン層、24はリンシリケ
ートガラスからなる層間絶縁膜、25は第2の低
抵抗ポリシリコン層、26はリンシリケートガラ
スからなるパツシベーシヨン膜26である。
SiO2膜21A上に配置された第2ポリシリコン
層25の一部分は、N+型拡散領域22をソース
領域とするMOS型トランジスタQのゲートとし
て作用するものであり、N+型ソース領域22は
デジツト線DGに接続される一方、第2ポリシリ
コン層25はワード層Wに接続される。トランジ
スタQのドレイン領域に相当する基板表面部分2
0Aは、SiO2膜21Aを介してその上に位置す
る第1ポリシリコン層23の一部分と共に情報蓄
積用コンデンサCを形成するもので、ポリシリコ
ン層23は電位源Vに接続される。コンデンサC
への情報電荷の書込みないしコンデンサCからの
情報電荷の読出しはトランジスタQのスイツチン
グ作用により制御される。 FIG. 2 shows the memory cell structure of a MOS type dynamic RAM (random access memory), and its equivalent circuit is shown in FIG.
20 is a P-type silicon substrate, on the surface of which a thick field SiO 2 film 21 is formed;
A thin SiO 2 film 21A is formed within the opening of the SiO 2 film 21. 22 is an N + type diffusion region, 23 is a first low-resistance polysilicon layer, 24 is an interlayer insulating film made of phosphosilicate glass, 25 is a second low-resistance polysilicon layer, and 26 is a passivation film made of phosphosilicate glass. It is 26.
A part of the second polysilicon layer 25 disposed on the SiO 2 film 21A acts as a gate of a MOS transistor Q whose source region is the N + type diffusion region 22. The second polysilicon layer 25 is connected to the word layer W while being connected to the digit line DG. Substrate surface portion 2 corresponding to the drain region of transistor Q
0A forms an information storage capacitor C together with a portion of the first polysilicon layer 23 located thereon via the SiO 2 film 21A, and the polysilicon layer 23 is connected to a potential source V. Capacitor C
The writing of information charges to or the reading of information charges from capacitor C is controlled by the switching action of transistor Q.
上記構成のメモリセルは、上述した半導体チツ
プ内に多数個形成されてRAMを構成するように
なつており、RAMの記憶容量が大きくなるほど
集積密度が増し、セルサイズが小さくなる。この
ため、例えば記憶容量が16Kビツト以上のMOS
型ダイナミツクRAMでは、コンデンサCのキヤ
パシタンスは非常に小さく、α線が基板表面領域
20Aに入射した際の電子−ホールペアの生成に
より容易に記憶情報が反転する事態が生じ、これ
がいわゆるソフト・エラーとなるわけである。 A large number of memory cells having the above configuration are formed in the semiconductor chip described above to constitute a RAM, and as the storage capacity of the RAM increases, the integration density increases and the cell size decreases. For this reason, for example, a MOS with a storage capacity of 16K bits or more
In the type dynamic RAM, the capacitance of the capacitor C is very small, and the generation of electron-hole pairs when α rays enter the substrate surface area 20A easily causes stored information to be reversed, resulting in a so-called soft error. That's why.
従つて、活性領域であるコンデンサ部に入射す
るα線量を低減することのできる本発明を上記の
ようなMOS型ダイナミツクRAMに適用すれば、
かようなソフト・エラーを防止することができる
ものである。 Therefore, if the present invention, which can reduce the amount of α-rays incident on the capacitor part which is the active region, is applied to the above-mentioned MOS type dynamic RAM,
Such soft errors can be prevented.
第4図は、本発明の他の適用対象としての
ECL(エミツタ・カツプルド・ロジツク)型式
のバイポーラ・ダイナミツクRAMのメモリセル
構造を等価回路で示したものである。図示のメモ
リセルは、マルチエミツタトランジスタQ1,Q2
及び抵抗R1,R2でフリツプフロツプを構成した
もので、Vccは電位源、ADはアドレス線、D,
Dはそれぞれデータ線を示す。このようなメモリ
セル構造を有するバイポーラRAMにおいても、
特に大容量・高集積度のものにおいては、α線照
射により生じた電子−ホールペアが容易にフリツ
プフロツプの状態を反転させ、ソフト・エラーを
ひき起こす。 FIG. 4 shows another application target of the present invention.
This is an equivalent circuit diagram of the memory cell structure of an ECL (emitter coupled logic) type bipolar dynamic RAM. The illustrated memory cells are multi-emitter transistors Q 1 , Q 2
and resistors R 1 and R 2 constitute a flip-flop, where Vcc is a potential source, AD is an address line, D,
Each D indicates a data line. Even in bipolar RAM with such a memory cell structure,
Particularly in large-capacity, highly integrated devices, electron-hole pairs generated by alpha ray irradiation easily reverse the state of the flip-flop, causing soft errors.
このようなソフト・エラーも前述のMOS型
RAMの場合と同様に本発明の適用により効果的
に防止することができるものである。 This kind of soft error is also the same as the MOS type mentioned above.
Similar to the case of RAM, this can be effectively prevented by applying the present invention.
第1図は、本発明の一実施例による半導体装置
を示す断面図、第2図は、本発明の適用対象であ
るMOS型RAMのメモリセル構造を示す基板断面
図、第3図は、第2図のメモリセルの等価回路
図、第4図は、本発明の他の適用対象としてのバ
イポーラ型RAMのメモリセル構造を示す等価回
路図である。
10……絶縁性ベース層、11,18……封止
ガラス層、14……半導体チツプ、16……α線
遮蔽用レジン層、17……絶縁性キヤツプ、19
……接着層、20……α線遮蔽体。
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a substrate showing a memory cell structure of a MOS RAM to which the present invention is applied, and FIG. FIG. 2 is an equivalent circuit diagram of the memory cell, and FIG. 4 is an equivalent circuit diagram showing the memory cell structure of a bipolar RAM to which the present invention is applied. 10... Insulating base layer, 11, 18... Sealing glass layer, 14... Semiconductor chip, 16... Alpha ray shielding resin layer, 17... Insulating cap, 19
... Adhesive layer, 20 ... α-ray shielding body.
Claims (1)
が固着されるベースと、前記半導体チツプの表面
をおおつて被着されたα線遮蔽用レジン層と、前
記ベースと共に前記チツプを収納するパツケージ
を構成すべく凹部を前記ベースに向けて該ベース
に重ね合わされるキヤツプと、前記パツケージ外
へ前記チツプ上の電極を電気的に導出する手段
と、前記キヤツプの凹部内面にα線遮蔽体とが設
けられていることを特徴とする半導体装置。1. A semiconductor chip, a base to which the back side of the semiconductor chip is fixed, an α-ray shielding resin layer deposited over the surface of the semiconductor chip, and a package for accommodating the chip together with the base. A cap stacked on the base with the recess facing the base, means for electrically leading out the electrodes on the chip to the outside of the package, and an α-ray shielding member provided on the inner surface of the recess of the cap. A semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3687779A JPS55130149A (en) | 1979-03-30 | 1979-03-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3687779A JPS55130149A (en) | 1979-03-30 | 1979-03-30 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55130149A JPS55130149A (en) | 1980-10-08 |
JPS6136709B2 true JPS6136709B2 (en) | 1986-08-20 |
Family
ID=12482004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3687779A Granted JPS55130149A (en) | 1979-03-30 | 1979-03-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55130149A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56137658A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
JPS61107119A (en) * | 1984-10-30 | 1986-05-26 | Hamamatsu Photonics Kk | Silicon photocell using ceramic container |
US4761335A (en) * | 1985-03-07 | 1988-08-02 | National Starch And Chemical Corporation | Alpha-particle protection of semiconductor devices |
JPS62115750A (en) * | 1985-11-15 | 1987-05-27 | Nec Corp | Semiconductor device |
US5264726A (en) * | 1989-07-21 | 1993-11-23 | Nec Corporation | Chip-carrier |
-
1979
- 1979-03-30 JP JP3687779A patent/JPS55130149A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS55130149A (en) | 1980-10-08 |
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