JPS6150349A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6150349A
JPS6150349A JP60161860A JP16186085A JPS6150349A JP S6150349 A JPS6150349 A JP S6150349A JP 60161860 A JP60161860 A JP 60161860A JP 16186085 A JP16186085 A JP 16186085A JP S6150349 A JPS6150349 A JP S6150349A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonded
active region
shielding plate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60161860A
Other languages
Japanese (ja)
Inventor
Takehisa Nitta
雄久 新田
Katsumi Ogiue
荻上 勝巳
Kanji Otsuka
寛治 大塚
Shinji Onishi
大西 新二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60161860A priority Critical patent/JPS6150349A/en
Publication of JPS6150349A publication Critical patent/JPS6150349A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent any erroneous operation due to alpha ray irradiation from happening by a method wherein a semiconductor chip is bonded on a substrate and then multiple electrodes on the chip are connected to corresponding external conductive means simultaneously bonding alpha ray shielding sheet on the surface of active region of semiconductor chip. CONSTITUTION:A semiconductor chip 14 is bonded on the surface of ceramics- made insulating base 10 through the intermediary of an adhesive layer 13 made of Au foil or Au metallized layer while multiple electrodes are electrically connected to corresponding leads 12 by bonding wires. An alpha ray shielding sheet 17 made of high purity (preferably exceeding 5-9) silicon several 100mum thick including the thickness of another adhesive layer 16 made of phosphorus silicide glass or lead glass etc. is bonded on the surface of active region of semiconductor chip 14 before or after wire bonding process while a ceramics-made insulating cap 18 is bonded on the base 10 through the intermediary of a low melting point glass layer 19.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法、特にダイナミックメモ
リ等の半導体素子を封止して成る半導体装置の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a semiconductor element such as a dynamic memory is sealed.

一般に、半導体素子は通常セラミック、ガラス若しくは
プラスチック(樹脂)等から成る封止体により封止され
る。これらの封止体(以下、パッケージと称す。)のう
ちとくにセラミックバック−ジにおけるセラミック材料
には数ppm程度のウラニウム(U)やトリウム(Th
)等が含まれている。これらの不純物は、例えば16t
hproc−ecdings of reliabii
ity physics(1978) ’tp88 K
述べられているように、α線を放出し、このα線によっ
てメモリ素子が誤動作してしまうことが知られている。
Generally, semiconductor elements are usually sealed with a sealing body made of ceramic, glass, plastic (resin), or the like. Among these sealed bodies (hereinafter referred to as packages), the ceramic material in the ceramic bag contains approximately several ppm of uranium (U) and thorium (Th).
) etc. are included. These impurities are, for example, 16t
hproc-ecdings of relayii
ity physics (1978) 'tp88 K
As mentioned above, it is known that alpha rays are emitted and memory devices malfunction due to these alpha rays.

このために、半導体素子の信頼性が著しく低下する場合
がある。
For this reason, the reliability of the semiconductor device may be significantly reduced.

U及びThの自然崩壊のエネルギー分布は4〜9MeV
であるがバ、ケージ材料中で発生したα線はその材料表
面に出るまでに分子との衝突でエネルギーを失うのでバ
、ケージから放射されるα線のエネルギー分布はO〜g
MeVとなる。
The energy distribution of spontaneous decay of U and Th is 4 to 9 MeV
However, the α rays generated in the cage material lose energy due to collisions with molecules before reaching the surface of the material, so the energy distribution of the α rays emitted from the cage is O to g.
MeV.

このα線がSiベレ、ト内に侵入すると電子を励起し、
少しづつエネルギーを失いながら走行する。従って、物
質中のα線の飛程は物質の密度に反比例し、初期エネル
ギーに比ajする。Si中では3.6eVの電子を励起
し5MeVのとき飛程は約25μmである。又、Si中
で電子が励起され1        ると、ホールも発
生することになり、電子−ホールのベアがα線の軌跡に
沿って発生することになる。こ°こで励起された電子数
Neはα線エネルギーが5 M e Vとすると、 Ne = 5MeV/ 8.6 eV =1.4 X 
10’個となる。これは0.22pグロンの電気量とな
る。
When this alpha ray enters the Si hole, it excites electrons,
It runs while losing energy little by little. Therefore, the range of α rays in a substance is inversely proportional to the density of the substance and is relative to the initial energy. In Si, electrons are excited at 3.6 eV, and at 5 MeV, the range is about 25 μm. Furthermore, when electrons are excited in Si, holes are also generated, and an electron-hole bear is generated along the locus of the α ray. The number of excited electrons Ne here is, assuming that the α-ray energy is 5 M e V, Ne = 5 MeV/ 8.6 eV = 1.4 X
There will be 10' pieces. This amounts to an amount of electricity of 0.22 pgrons.

以後濃度勾配による拡散と共に再結合により消滅するが
、この電荷がバイアスにより捕捉され、ベレットのある
境界条件の電荷量に比して無視できない値でちった時、
誤動作するわけである。この誤動作は素子の物理的性質
をそこなわずに起るためソフト・エラー(5oft  
Error)と呼ばれている。
Thereafter, the charge disappears due to diffusion and recombination due to the concentration gradient, but when this charge is captured by the bias and falls to a value that cannot be ignored compared to the amount of charge under a certain boundary condition of the pellet,
It will malfunction. This malfunction occurs without damaging the physical properties of the device, so it is a soft error (5of
Error).

のレジンコーティングを施すことがすでに提案されてい
る。しかしながら、この場合には、飼えば70μm以上
の所望の厚さで均一にレジンコーティングを施すのが困
難なこと、ワイヤボアディング後に半導体チップにレジ
ンコーティングを施すと組立歩留や信頼性を低下させや
すいことなどの欠点がある。
It has already been proposed to apply a resin coating. However, in this case, it is difficult to uniformly apply a resin coating to the desired thickness of 70 μm or more, and applying a resin coating to a semiconductor chip after wire boring may reduce assembly yield and reliability. It has drawbacks such as being easy to use.

高純度材料を半導体チップの活性領域を含む表面に直接
コートしてα線を防ぐ半導体装置の製造方法については
、特開昭55−088356に記載しである。
A method for manufacturing a semiconductor device that protects against alpha rays by directly coating the surface of a semiconductor chip, including the active region, with a high-purity material is described in Japanese Patent Laid-Open No. 55-088356.

本発明の目的は、このような欠点を伴うことなく活性領
域でのα線照射による誤動作を防止した半導体装置の製
造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents malfunctions due to alpha ray irradiation in the active region without having such drawbacks.

本発明による半導体装置の製造方法は、半導体チップを
基体に固着し、このチップ上に形成された電極と対応す
る外部との導通手段とを接続し、又、半導体チップの活
性領域表面にシリコンや石英などの高純度材料からなる
α線遮蔽板を貼付することを特徴とするもので、以下、
添付図面に示す実施例について詳述する。
In the method for manufacturing a semiconductor device according to the present invention, a semiconductor chip is fixed to a base, electrodes formed on the chip are connected to corresponding external conduction means, and silicon or silicon is applied to the surface of the active region of the semiconductor chip. It is characterized by attaching an α-ray shielding plate made of high-purity material such as quartz.
The embodiments shown in the accompanying drawings will be described in detail.

第1図は、本発明の一実施例に係る半導体装置を示すも
ので、セラミックス製の絶縁性ベース10の上面中央の
凹部底面上にはAuフォイル又はAu メタライズ層な
どからなる接着層13を介して半導体チップ14が固着
されている。この半導体チップ14は、例えばシリコン
からなり、その表面には後述するメモリセル等を含むα
線照射により誤動作しやすい活性領域が通常4〜5μm
の深さにわたりて形成されている。そして、半導体チッ
プ14上の多数の電極は、多数のボンディングワイヤに
より対応するり一ド12に電気的に接続される。
FIG. 1 shows a semiconductor device according to an embodiment of the present invention, in which an adhesive layer 13 made of an Au foil or an Au metallized layer is provided on the bottom of a recess at the center of the upper surface of an insulating base 10 made of ceramic. A semiconductor chip 14 is fixed thereto. This semiconductor chip 14 is made of silicon, for example, and includes α
The active area that is prone to malfunction due to radiation irradiation is usually 4 to 5 μm.
It is formed over a depth of . A large number of electrodes on the semiconductor chip 14 are electrically connected to corresponding leads 12 by a large number of bonding wires.

半導体チップ14の活性領域表面には、ワイヤボンディ
ングの前又は後に、例えばリンケイ酸ガラスあるいは鉛
ガラス等の接着層16により、数100μmの厚さの高
純度(好ましくはファイブ・ナイン以上)シリコンから
なるα線遮蔽板17が貼付される。
The surface of the active region of the semiconductor chip 14 is covered with an adhesive layer 16 of, for example, phosphosilicate glass or lead glass, made of high-purity (preferably five nines or more) silicon with a thickness of several hundred μm, before or after wire bonding. An α-ray shielding plate 17 is attached.

第2図は、遮蔽板17を貼付した後の半導体チップ14
の表面状態を示すもので、11はポンディングパッド(
電極)である。この7リコ/製のα線遮蔽板17はその
表面に前もって表面酸化処理を施し、絶縁性を付与して
おくのが好ましい。
FIG. 2 shows the semiconductor chip 14 after the shielding plate 17 has been attached.
11 indicates the surface condition of the bonding pad (
electrode). It is preferable that the surface of the α-ray shielding plate 17 manufactured by 7 Rico Co., Ltd. be subjected to surface oxidation treatment in advance to impart insulation properties.

なお、α線遮蔽板17としては、この他にも表面酸化し
たアルミニウム板、石英板、テフロン(商品名)等のフ
、素樹脂又はポリイミド・インインドロ・キナゾリンデ
ィオン(PIポリマーと称す)等のポリイミド系樹脂か
らなる板材などを用いることができる。ここで、テフロ
ン板は、スピンオン法で被着したガラス又はPIポリマ
ーで貼付するのがよい。また、接着層16として、乾燥
が必要な接着材を使用した場合VCは、α線遮蔽板17
に予め多数の小孔を設け、メツシー状等に加工しておい
てもよく、このようにすれば、乾燥が容易になる効果が
ある。
In addition, the α-ray shielding plate 17 may also be made of surface-oxidized aluminum plate, quartz plate, fluorine such as Teflon (trade name), base resin, or polyimide such as polyimide-indo-quinazolindion (referred to as PI polymer). A plate material made of resin can be used. Here, the Teflon plate is preferably attached with glass or PI polymer applied by a spin-on method. In addition, when an adhesive material that requires drying is used as the adhesive layer 16, the VC
A large number of small holes may be provided in advance and processed into a mesh shape, etc., and this has the effect of facilitating drying.

一方、セラミ、り製の絶縁性キャップ18は一方の主面
の中央部に凹部18aを有し、との凹部18aを半導体
チップ14に対向させるようにしてベース10に重ね合
わされるものでちる。キャップ18のベース10との対
向接合面には予め低融点ガラス層19が被着されており
、ベース10にキャップ18を重ね合わせた後、封止用
ガラス層19の融点まで加熱し、冷却することによりベ
ース10とキャップ18とが相互に接着される。
On the other hand, the insulating cap 18 made of ceramic or resin has a recess 18a in the center of one main surface, and is placed over the base 10 with the recess 18a facing the semiconductor chip 14. A low melting point glass layer 19 is previously applied to the joint surface of the cap 18 facing the base 10, and after the cap 18 is superimposed on the base 10, it is heated to the melting point of the sealing glass layer 19 and then cooled. As a result, the base 10 and the cap 18 are bonded to each other.

1          上記構成において、α線はベー
ス10及びキャップ18のセラミックスと、封止ガラス
層11゜19のガラスとかち放射されるが、このうち、
ベース10から放射されるα線は半導体チップ14が1
50〜500μmの厚さを有するためチップ表面の活性
領域に到達するまでにはその誤動作を生じさせえない程
度に弱められているので殆ど問題にならない。そこで、
問題となるのは、キャップ18及び封止ガラス層11,
19からのα線であるが、キャップ18からのα線は遮
蔽板17で十分弱められると共に、封止ガラス層11.
17からのα線もチップ表面の活性領域に対する入射角
が比較的大きいものは遮蔽板17で十分弱められるつそ
して、封止ガラス層11.19から放射されたα線のう
ち、遮蔽板17を経由しないようにチップ14の側方か
ら活性領域に入射するα線は、入射角が浅いことから活
性領域に対する作用力が本来あまり強くないので殆ど問
題にならない場合が多い。
1 In the above configuration, alpha rays are emitted from the ceramics of the base 10 and the cap 18, and the glass of the sealing glass layer 11.
The α rays emitted from the base 10 are absorbed by the semiconductor chip 14.
Since it has a thickness of 50 to 500 μm, by the time it reaches the active region on the chip surface, it is weakened to such an extent that it will not cause malfunction, so it will hardly be a problem. Therefore,
The problem is that the cap 18 and the sealing glass layer 11,
However, the α rays from the cap 18 are sufficiently weakened by the shielding plate 17, and the α rays from the sealing glass layer 11.
The shielding plate 17 sufficiently weakens alpha rays from the shielding plate 17 that have a relatively large incident angle with respect to the active region on the chip surface. The α rays that enter the active region from the sides of the chip 14 without passing through the α rays have a shallow angle of incidence, so the acting force on the active region is originally not very strong, so in many cases it does not pose a problem.

従って、上記した本発明の半導体装置の製造方法によi
ば、α線による活性領域での誤動作を効果的に防止する
ことができる。また、遮蔽板17は予め成形されている
ので、厚さのばらつきは従来の単なるレジン塗布の場合
に比べて非常に少ない利点がある。その上、遮蔽板17
はチップ表面を保護する作用もはだすので、例えば半導
体チップ14の取扱いにあたって真空チャック等で遮蔽
板17を直接に吸着することができ、チップ14の取扱
いが容易になる利点もある。なお、遮蔽板17のチップ
14への貼付けは、チップ14がウェハの一領域をなし
ているウェハ状態においてもこれを行うことができ、ウ
ェハ検査において良品と判定されたチップ領域にのみ遮
蔽板17を選択的に貼付け、しかる後、ウェハを分断し
て個々のチップを得るようにしてもよい。この場合の作
業においても遮蔽板17はチップ領域又はチップを外界
から化学的ないし物理的に保護することができるもので
ある。
Therefore, by the method for manufacturing a semiconductor device of the present invention described above, i.
For example, malfunctions in the active region due to α rays can be effectively prevented. Furthermore, since the shielding plate 17 is pre-formed, there is an advantage that variations in thickness are much smaller than in the conventional case of mere resin coating. Moreover, the shielding plate 17
Since it also has the effect of protecting the chip surface, for example, when handling the semiconductor chip 14, the shielding plate 17 can be directly adsorbed with a vacuum chuck or the like, which has the advantage of making the chip 14 easier to handle. Note that the shielding plate 17 can be attached to the chip 14 even in a wafer state where the chip 14 forms one area of the wafer, and the shielding plate 17 can be attached only to the chip area determined to be good in the wafer inspection. The wafer may be selectively attached and then the wafer may be separated to obtain individual chips. Even in this case, the shielding plate 17 can chemically or physically protect the chip area or the chip from the outside world.

ところで、本発明の適用対象となる半導体装置は、前述
したようにα線照射により誤動作することのある活性領
域が形成された半導体チップを有するものであるが、次
にその具体例をいくつか説明する。
By the way, as mentioned above, the semiconductor device to which the present invention is applied has a semiconductor chip in which an active region is formed that may malfunction due to alpha ray irradiation.Next, some specific examples will be explained. do.

第3図は、MO8O8型ダイアミRAM(ランダム・ア
クセス・メモリ)のメモリセル構造を示すもので、その
等何回路は第4図に示されている。
FIG. 3 shows the memory cell structure of a MO8O8 type diami RAM (random access memory), and its circuits are shown in FIG.

20はP型/リコン基板で、その表面には厚いフィール
ドS i O,膜21が形成されると共に、この5in
2膜21の開口部内には薄い5in2 膜21Aが形成
されている。22はN+型拡散領域、23は第1の低抵
抗ポリシリコン層、241dリンシリケートガラスから
なる眉間絶縁膜、25は第2の低抵抗ポリノリコン層、
26はリンシリク−トガラスからなるパ、シベーシ1ン
膜でちる。SiO□膜21膜上1A上された第2ポリシ
リコン層25の一部分は、N+型拡散領域22をソース
領域とするMO8型トランジスタQのゲートとして作用
するものでちり、N+型ノース領域22はデジット線D
GK接続される一方、第2ポリシリコン層25はワード
線Wに接続される。トランジスタQのドレイン領域に相
当する基板表面部分20Aは、5in2膜21Aを介し
てその上に位置する第1ポリシリコン層23の一部分と
共に情報蓄積用コンデンサCを形成するもので、ポリシ
リコン層23は電位源■に接続される。コンデンサCへ
の情報電荷の書込みないしコンデンサCからの情報電荷
の読出しはトランジスタQのスイッチング作用により制
御される。
20 is a P type/recon substrate, on the surface of which a thick field SiO film 21 is formed, and this 5 inch
A thin 5 in 2 film 21A is formed within the opening of the 2 film 21. 22 is an N+ type diffusion region, 23 is a first low resistance polysilicon layer, 241d is an insulating film between the eyebrows made of phosphorus silicate glass, 25 is a second low resistance polysilicon layer,
Reference numeral 26 is made of a glass film made of phosphorous glass. A part of the second polysilicon layer 25 deposited 1A on the SiO□ film 21 acts as a gate of an MO8 type transistor Q whose source region is the N+ type diffusion region 22, and the N+ type north region 22 is a digit part. Line D
GK connection, while second polysilicon layer 25 is connected to word line W. The substrate surface portion 20A corresponding to the drain region of the transistor Q forms an information storage capacitor C together with a portion of the first polysilicon layer 23 located thereon via the 5in2 film 21A. Connected to potential source ■. The writing of information charges into the capacitor C and the reading of information charges from the capacitor C are controlled by the switching action of the transistor Q.

上記構成のメモリセルは、前述した半導体チップ内に多
数個形成されてRAMを構成するようになっており、R
A Mの記憶容量が大きくなるほど集積密度が増し、セ
ルサイズが小さくなる。このため、91Jえは記憶容量
が16にビット以上のMO’S型ダイ型ダイノミAMで
は、コンデンサCのキャパシタンスは非常に小さく、α
線が基板表面領域20AK入射した際の電子−ホールペ
アの生成によシ容易に記憶情報が反転する事態が生じ、
これがいわゆるソフト・エラーとなるわけである。
A large number of memory cells having the above configuration are formed in the semiconductor chip described above to constitute a RAM.
The larger the storage capacity of an AM, the higher the integration density and the smaller the cell size. For this reason, in the MO'S die-type Dyno AM with a storage capacity of 16 bits or more, the capacitance of the capacitor C is very small, and α
Due to the generation of electron-hole pairs when the wire enters the substrate surface area 20AK, a situation arises in which stored information is easily reversed.
This is what is called a soft error.

従って、活性領域であるコンデンサ部に入射するα線量
を低減することのできる本発明を上記の1      
  ようなMO8型タ°イナミックRAMに適用すれば
、かようなソフト・エラーを防止することができるもの
である。
Therefore, the present invention, which can reduce the amount of α-rays incident on the capacitor part which is the active region, is
If applied to such an MO8 type dynamic RAM, such soft errors can be prevented.

第5図は、本発明の他の適用対象としてのECL(エミ
ッタ・カップルド・ロジック)型式のバイポーラ・ダイ
ナミックRAMのメモリセル構造を等両回路で示したも
のである。図示のメモリセルは、マルチエミッタトラン
ジスタQ、、Q、及び抵抗R,,R2でクリップ70ツ
ブを構成したもので、ycCは電位源、ADはアドレス
線、 D、Dはそれぞれデータ線を示す。このようなメ
モリセル構造を有するバイポーラRAMにおいても、特
に大容量・高集積度のものにおいては、α線照射により
生じた電子−ホールベアが容易に7リツプ70ツブの状
態を反転させ、ソフト・エラーをひき起こす。
FIG. 5 shows the memory cell structure of an ECL (emitter coupled logic) type bipolar dynamic RAM, which is another application of the present invention, using both circuits. The illustrated memory cell has a clip 70 block made up of multi-emitter transistors Q, , Q and resistors R, , R2, where ycC is a potential source, AD is an address line, and D and D are data lines, respectively. Even in bipolar RAMs with such a memory cell structure, especially those with large capacity and high integration, electron-hole bears generated by alpha ray irradiation can easily reverse the 7-lip and 70-tub state, resulting in soft errors. cause

このようなソフト・エラーも前述のMO8型RAMの場
合と同様に本発明の適用により効果的に防止することが
できるものである。
Such soft errors can also be effectively prevented by applying the present invention, as in the case of the MO8 type RAM described above.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例に係る半導体装置を示す断
面図、 第2図は、α線遮蔽板を固着した半導体チップの上面図
、 第3図は、本発明の適用対象であるMO8型RAMのメ
モリセル構造を示す基板断面図、第4図は、第3図のメ
モリセルの等価回路図、第5図は、本発明の他の適用対
象としてのバイポーラ型RAMのメモリセル構造を示す
等価回路図である。 10・・・絶縁性ベース、11,19・・・封止ガラス
層、14・・・半導体チップ、16・・・α線遮蔽板、
18・・・絶縁性キャップ。 第  1  図 第  2  図
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a top view of a semiconductor chip to which an α-ray shielding plate is fixed, and FIG. 3 is an object to which the present invention is applied. 4 is an equivalent circuit diagram of the memory cell of FIG. 3, and FIG. 5 is a memory cell structure of a bipolar RAM as another application target of the present invention. FIG. 10... Insulating base, 11, 19... Sealing glass layer, 14... Semiconductor chip, 16... α-ray shielding plate,
18...Insulating cap. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 1、(a)電極と活性領域とを持つ半導体ペレットを用
意する工程と (b)上記半導体ペレットを載置する基体を用意する工
程と (c)少なくともその表面に絶縁性を有するα線遮蔽体
を用意する工程と (d)上記半導体ペレットを上記基体に固着する工程と (e)少なくとも上記半導体ペレットの活性領域表面に
上記少なくともその表面に絶縁性を有するα線遮蔽板を
貼付ける工程と (f)上記半導体ペレットの電極と対応する外部との導
通手段とを接続する工程と (g)上記半導体ペレット、上記基体、上記少なくとも
その表面に絶縁性を有するα線遮蔽板そして外部との導
通手段の少なくとも一部を封止体により封止する工程と からなることを特徴とする半導体装置の製造方法。 2、上記封止体は、セラミック製の絶縁性キャップとセ
ラミック製の絶縁性ベースとからなり、上記外部との導
通手段は、上記セラミック製の絶縁性キャップと上記セ
ラミック製の絶縁性ベースとの間に封止ガラス層を介し
て接着されたリードであることを特徴とする特許請求の
範囲第1項記載の半導体装置の製造方法。 3、上記少なくともその表面に絶縁性を有するα線遮蔽
板は、ポリイミド系樹脂からなることを特徴とする特許
請求の範囲第1項記載の半導体装置の製造方法。
[Claims] 1. (a) a step of preparing a semiconductor pellet having an electrode and an active region; (b) a step of preparing a base on which the semiconductor pellet is placed; and (c) an insulating material on at least the surface thereof. (d) fixing the semiconductor pellet to the substrate; and (e) providing an α-ray shielding plate having an insulating property on at least the surface of the active region of the semiconductor pellet. (f) connecting the electrodes of the semiconductor pellet to a corresponding external conduction means; and (g) the semiconductor pellet, the substrate, and an α-ray shielding plate having an insulating property on at least its surface. A method for manufacturing a semiconductor device, comprising the step of sealing at least a portion of the means for communicating with the outside with a sealing body. 2. The sealing body is composed of a ceramic insulating cap and a ceramic insulating base, and the means for communicating with the outside is a connection between the ceramic insulating cap and the ceramic insulating base. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the leads are bonded with a sealing glass layer interposed therebetween. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the α-ray shielding plate having insulating properties at least on its surface is made of polyimide resin.
JP60161860A 1985-07-24 1985-07-24 Manufacture of semiconductor device Pending JPS6150349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60161860A JPS6150349A (en) 1985-07-24 1985-07-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60161860A JPS6150349A (en) 1985-07-24 1985-07-24 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3547779A Division JPS55128845A (en) 1979-03-28 1979-03-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6150349A true JPS6150349A (en) 1986-03-12

Family

ID=15743333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60161860A Pending JPS6150349A (en) 1985-07-24 1985-07-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6150349A (en)

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