JPH01235363A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01235363A
JPH01235363A JP63063907A JP6390788A JPH01235363A JP H01235363 A JPH01235363 A JP H01235363A JP 63063907 A JP63063907 A JP 63063907A JP 6390788 A JP6390788 A JP 6390788A JP H01235363 A JPH01235363 A JP H01235363A
Authority
JP
Japan
Prior art keywords
pellet
semiconductor chip
bonding
bonded
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63063907A
Other languages
Japanese (ja)
Inventor
Ichiro Anjo
Kunihiko Nishi
Susumu Okikawa
Hajime Iijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63063907A priority Critical patent/JPH01235363A/en
Publication of JPH01235363A publication Critical patent/JPH01235363A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE: To increase the mounting density per package by a method wherein one or more semiconductor chips are piled up on a semiconductor chip and these are pellet-bonded by using a nonconducting adhesive.
CONSTITUTION: A lower-part semiconductor chip 1B is pellet-bonded to a tab 2 by using an adhesive 3 for pellet bonding use. An upper-part semiconductor chip 1A is pellet-bonded to the lower-part semiconductor chip 1B by using a nonconducting adhesive 4 for pellet bonding use. The upper-part and lower- part semiconductor chips 1A and 1B are connected individually to lead frames 6 by using bonding wires 5A, 5B, and sealed by using a resin 7 for mold sealing use such as a resin or the like. Individual pads on the upper-part and lower-part semiconductor chips 1A and 1B and the bonding wires 5A, 5B are connected by a wedge ball bonding method. The lead frames 6 and the bonding wires 5A, 5B are connected by a thermal pressure bonding method used together with an ultrasonic oscillation. By this setup, the mounting density per package can be increased by a portion where a semiconductor chip is piled up at the upper-part.
COPYRIGHT: (C)1989,JPO&Japio
JP63063907A 1988-03-16 1988-03-16 Semiconductor device Pending JPH01235363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63063907A JPH01235363A (en) 1988-03-16 1988-03-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63063907A JPH01235363A (en) 1988-03-16 1988-03-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01235363A true JPH01235363A (en) 1989-09-20

Family

ID=13242867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63063907A Pending JPH01235363A (en) 1988-03-16 1988-03-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01235363A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06224362A (en) * 1992-10-28 1994-08-12 Internatl Business Mach Corp <Ibm> Lead frame package for electronic device
US5381047A (en) * 1992-05-27 1995-01-10 Kanno; Kazumasa Semiconductor integrated circuit having multiple silicon chips
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
WO2000033379A1 (en) * 1998-12-02 2000-06-08 Hitachi, Ltd. Semiconductor device, method of manufacture thereof, and electronic device
KR20010064907A (en) * 1999-12-20 2001-07-11 마이클 디. 오브라이언 wire bonding method and semiconductor package using it
JP2001274315A (en) * 2000-03-24 2001-10-05 Sony Corp Semiconductor device and its manufacturing method
JP2008078367A (en) * 2006-09-21 2008-04-03 Renesas Technology Corp Semiconductor device
JP2009260373A (en) * 2009-07-27 2009-11-05 Fujitsu Microelectronics Ltd Semiconductor device, its method for manufacturing, and semiconductor substrate

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5495398A (en) * 1992-05-22 1996-02-27 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5502289A (en) * 1992-05-22 1996-03-26 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
KR100282285B1 (en) * 1992-05-22 2001-02-15 클라크 3세 존 엠. Stacked multichip module and manufacturing method thereof
US5381047A (en) * 1992-05-27 1995-01-10 Kanno; Kazumasa Semiconductor integrated circuit having multiple silicon chips
JPH06224362A (en) * 1992-10-28 1994-08-12 Internatl Business Mach Corp <Ibm> Lead frame package for electronic device
WO2000033379A1 (en) * 1998-12-02 2000-06-08 Hitachi, Ltd. Semiconductor device, method of manufacture thereof, and electronic device
KR20010064907A (en) * 1999-12-20 2001-07-11 마이클 디. 오브라이언 wire bonding method and semiconductor package using it
JP2001274315A (en) * 2000-03-24 2001-10-05 Sony Corp Semiconductor device and its manufacturing method
JP2008078367A (en) * 2006-09-21 2008-04-03 Renesas Technology Corp Semiconductor device
US8518744B2 (en) 2006-09-21 2013-08-27 Renesas Electronics Corporation Method of manufacturing semiconductor device
JP2009260373A (en) * 2009-07-27 2009-11-05 Fujitsu Microelectronics Ltd Semiconductor device, its method for manufacturing, and semiconductor substrate

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