JPS627700B2 - - Google Patents
Info
- Publication number
- JPS627700B2 JPS627700B2 JP3547879A JP3547879A JPS627700B2 JP S627700 B2 JPS627700 B2 JP S627700B2 JP 3547879 A JP3547879 A JP 3547879A JP 3547879 A JP3547879 A JP 3547879A JP S627700 B2 JPS627700 B2 JP S627700B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- rays
- active region
- semiconductor device
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 6
- 239000002245 particle Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000011230 binding agent Substances 0.000 claims description 5
- 239000010453 quartz Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 21
- 230000005260 alpha ray Effects 0.000 description 11
- 230000007257 malfunction Effects 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000005394 sealing glass Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052776 Thorium Inorganic materials 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 210000004013 groin Anatomy 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にダイナミツクメモリ
等の半導体素子を封止して成る半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device formed by sealing a semiconductor element such as a dynamic memory.
一般に、半導体素子は通常セラミツク、ガラス
若しくはプラスチツク(樹脂)等から成る封止体
により封止される。これらの封止体(以下、パツ
ケージと称す。)のうちとくにセラミツクパツケ
ージにおけるセラミツク材料には数ppm程度の
ウラニウム(U)やトリウム(Th)等が含まれ
ている。これらの不純物は、例えば16th
procecdings of reliability physics(1978)、P38
に述べられているように、α線を放出し、このα
線によつてメモリ素子が誤動作してしまうことが
知られている。このために、半導体素子の信頼性
が著しく低下する場合がある。 In general, semiconductor elements are usually sealed with a sealing body made of ceramic, glass, plastic (resin), or the like. Among these sealed bodies (hereinafter referred to as packages), the ceramic materials of ceramic packages in particular contain about several ppm of uranium (U), thorium (Th), and the like. These impurities are e.g.
proceedings of reliability physics (1978), P38
As described in
It is known that wires can cause memory devices to malfunction. For this reason, the reliability of the semiconductor device may be significantly reduced.
U及びThの自然崩壊のエネルギー分布は4〜
9MeVであるがパツケージ材料中で発生したα線
はその材料表面に出るまでに分子との衝突でエネ
ルギーを失うのでパツケージから放射されるα線
のエネルギー分布は0〜9MeVとなる。 The energy distribution of spontaneous decay of U and Th is 4~
Although the α rays generated in the package material lose energy due to collisions with molecules before reaching the surface of the material, the energy distribution of the α rays emitted from the package is 0 to 9 MeV.
このα線がSiペレツト内に侵入すると電子を励
起し、少しづつエネルギーを失いながら走行す
る。従つて、物質中のα線の飛程は物質の密度に
反比例し、初期エネルギーに比例する。Si中では
3.6eVの電子を励起し5MeVのとき飛程は約25μ
mである。又、Si中で電子が励起されると、ホー
ルも発生することになり、電子−ホールのペアが
α線の軌跡に沿つて発生することになる。ここで
励起された電子数Neはα線エネルギーが5MeVと
すると、
Ne5MeV/3.6eV=1.4×106個
となる。これは0.22Pグロンの電気量となる。以
後濃度勾配による拡散と共に再結合により消滅す
るが、この電荷がバイアスにより補捉され、ペレ
ツトのある境界条件の電荷量に比して無視できな
い値であつた時、誤動作するわけである。この誤
動作は素子の物理的性質をそこなわずに起るため
ソフト・エラー(Soft Error)と呼ばれている。 When this alpha ray enters the Si pellet, it excites electrons and travels while gradually losing energy. Therefore, the range of alpha rays in a substance is inversely proportional to the density of the substance and proportional to its initial energy. In Si
When exciting electrons at 3.6eV and 5MeV, the range is about 25μ
It is m. Moreover, when electrons are excited in Si, holes are also generated, and electron-hole pairs are generated along the locus of the α ray. The number of excited electrons Ne here is Ne5MeV/3.6eV=1.4×10 6 when the α-ray energy is 5MeV. This is the amount of electricity of 0.22P groins. Thereafter, the charge disappears due to diffusion and recombination due to the concentration gradient, but this charge is captured by the bias, and when it reaches a value that cannot be ignored compared to the amount of charge under a certain boundary condition of the pellet, a malfunction occurs. This malfunction is called a soft error because it occurs without damaging the physical properties of the device.
このような誤動作を防止するため、半導体チツ
プの活性領域表面にα線遮蔽用のレジンコーテイ
ングを施すことがすでに提案されている。しかし
ながら、この場合には、例えば70μm以上の所望
の厚さで均一にレジンコーテイングを施すのが容
易でないという問題点がある。 In order to prevent such malfunctions, it has already been proposed to apply a resin coating to the surface of the active region of a semiconductor chip for shielding alpha rays. However, in this case, there is a problem that it is not easy to apply a uniform resin coating to a desired thickness of, for example, 70 μm or more.
本発明の目的は、このような問題点を解消し、
活性領域でのα線照射による誤動作を防止した半
導体装置を提供することにある。 The purpose of the present invention is to solve these problems,
An object of the present invention is to provide a semiconductor device that prevents malfunctions caused by alpha ray irradiation in an active region.
本発明による半導体装置は、半導体チツプの活
性領域表面にバインダーでといたシリコン又は石
英の高純度材料の粒子からなるα線遮蔽層を被着
したことを特徴とするもので、以下、添付図面に
示す実施例について詳述する。 A semiconductor device according to the present invention is characterized in that an α-ray shielding layer made of particles of a high-purity silicon or quartz material mixed with a binder is deposited on the surface of an active region of a semiconductor chip. The illustrated embodiment will be described in detail.
第1図は、本発明の一実施例による半導体装置
を示すもので、セラミツク製の絶縁性ベース10
の上面中央の凹部底面上にはAuフオイル又はAu
メタライズ層などからなる接着層13を介して半
導体チツプ14が固着されている。この半導体チ
ツプ14は、例えばシリコンからなり、その表面
には後述するメモリセル等を含むα線照射により
誤動作しやすい活性領域が通常4〜5μmの深さ
にわたつて形成されている。そして、半導体チツ
プ14上の多数の電極は、多数のボンデイングワ
イヤにより対応するリード12に電気的に接続さ
れる。 FIG. 1 shows a semiconductor device according to an embodiment of the present invention, in which an insulating base 10 made of ceramic
There is Au foil or Au on the bottom of the recess in the center of the top surface.
A semiconductor chip 14 is fixed via an adhesive layer 13 made of a metallized layer or the like. The semiconductor chip 14 is made of silicon, for example, and has an active region on its surface that is usually 4 to 5 .mu.m deep and is prone to malfunction when irradiated with alpha rays, including memory cells, which will be described later. A large number of electrodes on the semiconductor chip 14 are electrically connected to corresponding leads 12 by a large number of bonding wires.
半導体チツプ14の活性領域表面には、高純度
(好ましくはフアイブ・ナイン以上)シリコンの
粒子(ビーズ)をバインダーとしての高純度(金
属類を含まない)のスピンオンガラスでといたも
のからなるα線遮蔽層16が被着される。このよ
うな遮蔽層16の被着は、ワイヤボンデイングの
終了後に行なわれるが、ワイヤボンデイングの前
にチツプ状態もしくはウエハ状態において局部的
に実施することもできる。ここで、バインダーと
しては、ポリイミド・イソインドロ・キナゾリン
デイオン等のポリイミド系樹脂を用いることもで
きる。また、α線遮蔽層を構成する高純度粒子と
しては石英ビーズ等も使用できる。 The surface of the active region of the semiconductor chip 14 is coated with alpha rays made of particles (beads) of high-purity (preferably five nines or higher) silicon bound with high-purity (no metals included) spin-on glass as a binder. A shielding layer 16 is applied. The application of such a shielding layer 16 is carried out after the completion of wire bonding, but it can also be carried out locally in the chip or wafer state before wire bonding. Here, as the binder, polyimide resins such as polyimide, isoindolo, quinazolinedeion, etc. can also be used. Furthermore, quartz beads or the like can be used as the high-purity particles constituting the α-ray shielding layer.
シリコン又は石英の粒子を得るには、それらの
材料を粉砕した後、エツチング洗滌を複数回くり
かえす方法をとることができる。 Silicon or quartz particles can be obtained by pulverizing these materials and then repeating the etching process several times.
α線遮蔽層16は、数10〜数100μmの厚さに
ほぼ均一に被着することができ、被着後は適当な
熱処理により被着層の固化ないし乾燥を図るよう
にする。 The α-ray shielding layer 16 can be applied almost uniformly to a thickness of several tens to several hundred μm, and after being applied, the adhered layer is solidified or dried by an appropriate heat treatment.
一方、セラミツク製の絶縁性キヤツプ17は一
方の主面の中央部に凹部17aを有し、この凹部
17aを半導体チツプ14に対向させるようにし
てベース10に重ね合わされるものである。キヤ
ツプ16のベース10との対向接合面には予め低
融点ガラス層18が被着されており、ベース10
にキヤツプ17を重ね合わせた後、封止用ガラス
層18の融点まで加熱し、冷却することによりベ
ース10とキヤツプ17とが相互に接着される。 On the other hand, the insulating cap 17 made of ceramic has a recess 17a in the center of one main surface, and is superimposed on the base 10 with the recess 17a facing the semiconductor chip 14. A low melting point glass layer 18 is previously applied to the joint surface of the cap 16 facing the base 10.
After the cap 17 is superimposed on the base 10 and the cap 17, the base 10 and the cap 17 are bonded to each other by heating the sealing glass layer 18 to its melting point and cooling it.
上記構成において、α線はベース10及びキヤ
ツプ17のセラミツクスと、封止ガラス層11,
18のガラスとから放射されるが、このうち、ベ
ース10から放射されるα線は半導体チツプ14
が150〜500μmの厚さを有するためチツプ表面の
活性領域に到達するまでにはその誤動作を生じさ
せえない程度に弱められているので殆ど問題にな
らない。そこで、問題となるのは、キヤツプ17
及び封止ガラス層11,18からのα線である
が、これらのα線は、遮蔽層16が半導体チツプ
14の側面及び上面をおおつて形成されているた
め遮蔽層16で十分減衰され、半導体チツプ14
の活性領域に入射するα線量は実質的に無視でき
るようになる。 In the above configuration, the α rays are transmitted to the ceramics of the base 10 and the cap 17, the sealing glass layer 11,
Among them, alpha rays emitted from the base 10 are emitted from the semiconductor chip 14.
Since it has a thickness of 150 to 500 μm, by the time it reaches the active region on the chip surface, it has been weakened to the extent that it will not cause any malfunction, so it poses little problem. Therefore, the problem is that cap 17
and α rays from the sealing glass layers 11 and 18, but since the shielding layer 16 is formed to cover the side and top surfaces of the semiconductor chip 14, these α rays are sufficiently attenuated by the shielding layer 16, and are not absorbed by the semiconductor chip. Chip 14
The amount of alpha radiation incident on the active region becomes virtually negligible.
従つて、上記した本発明の半導体装置によれ
ば、α線による活性領域での誤動作を効果的に防
止することができる。その上、α線遮蔽層16が
バインダーでといた高純度材料粒子からなつてい
るため所望の厚さに均一に形成しやすい利点もあ
る。 Therefore, according to the semiconductor device of the present invention described above, malfunctions in the active region due to α rays can be effectively prevented. Furthermore, since the α-ray shielding layer 16 is made of high-purity material particles mixed with a binder, it has the advantage that it can be easily formed to a desired thickness uniformly.
ところで、本発明の適用対象となる半導体装置
は、前述したようにα線照射により誤動作するこ
とのある活性領域が形成された半導体チツプを有
するものであるが、次にその具体例をいくつか説
明する。 By the way, as mentioned above, the semiconductor device to which the present invention is applied has a semiconductor chip in which an active region is formed that may malfunction due to alpha ray irradiation.Next, some specific examples will be explained. do.
第2図は、MOS型ダイナミツクRAM(ランダ
ム・アクセス・メモリ)のメモリセル構造を示す
もので、その等価回路は第3図に示されている。
20はP型シリコン基板で、その表面には厚いフ
イールドSiO2膜21が形成されると共に、この
SiO2膜21の開口部内には薄いSiO2膜21Aが
形成されている。22はN+型拡散領域、23は
第1の低抵抗ポリシリコン層、24はリンシリケ
ートガラスからなる層間絶縁膜、25は第2の低
抵抗ポリシリコン層、26はリンシリケートガラ
スからなるパツシベーシヨン膜である。SiO2膜
21A上に配置された第2ポリシリコン層25の
一部分は、N+型拡散領域22をソース領域とす
るMOS型トランジスタQのゲートとして作用す
るものであり、N+型ソース領域22はデジツト
線DGに接続される一方、第2ポリシリコン層2
5はワード線Wに接続される。トランジスタQの
ドレイン領域に相当する基板表面部分20Aは、
SiO2膜21Aを介してその上に位置する第1ポ
リシリコン層23の一部分と共に情報蓄積用コン
デンサCを形成するもので、ポリシリコン層23
は電位源Vに接続される。コンデンサCへの情報
電荷の書込みないしコンデンサCからの情報電荷
の読出しはトランジスタQのスイツチング作用に
より制御される。 FIG. 2 shows the memory cell structure of a MOS type dynamic RAM (random access memory), and its equivalent circuit is shown in FIG.
20 is a P-type silicon substrate, on the surface of which a thick field SiO 2 film 21 is formed;
A thin SiO 2 film 21A is formed within the opening of the SiO 2 film 21. 22 is an N + type diffusion region, 23 is a first low-resistance polysilicon layer, 24 is an interlayer insulating film made of phosphosilicate glass, 25 is a second low-resistance polysilicon layer, and 26 is a passivation film made of phosphosilicate glass. It is. A part of the second polysilicon layer 25 disposed on the SiO 2 film 21A acts as a gate of a MOS transistor Q whose source region is the N + type diffusion region 22. While connected to the digit line DG, the second polysilicon layer 2
5 is connected to word line W. The substrate surface portion 20A corresponding to the drain region of the transistor Q is
An information storage capacitor C is formed together with a portion of the first polysilicon layer 23 located thereon via the SiO 2 film 21A.
is connected to a potential source V. The writing of information charges into the capacitor C and the reading of information charges from the capacitor C are controlled by the switching action of the transistor Q.
上記構成のメモリセルは、前述した半導体チツ
プ内に多数個形成されてRAMを構成するように
なつており、RAMの記憶容量が大きくなるほど
集積密度が増し、セルサイズが小さくなる。この
ため、例えば記憶容量が16Kビツト以上のMOS
型ダイナミツクRAMでは、コンデンサCのキヤ
パシタンスは非常に小さく、α線が基板表面領域
20Aに入射した際の電子−ホールペアの生成に
より容易に記憶情報が反転する事態が生じ、これ
がいわゆるソフト・エラーとなるわけである。 A large number of memory cells having the above configuration are formed in the semiconductor chip described above to constitute a RAM, and as the storage capacity of the RAM increases, the integration density increases and the cell size decreases. For this reason, for example, a MOS with a storage capacity of 16K bits or more
In type dynamic RAM, the capacitance of capacitor C is very small, and the generation of electron-hole pairs when α rays enter the substrate surface area 20A can easily cause stored information to be reversed, resulting in a so-called soft error. That's why.
従つて、活性領域であるコンデンサ部に入射す
るα線量を低減することのできる本発明を上記の
ようなMOS型ダイナミツクRAMに適用すれば、
かようなソフト・エラーを防止することができる
ものである。 Therefore, if the present invention, which can reduce the amount of α-rays incident on the capacitor part which is the active region, is applied to the above-mentioned MOS type dynamic RAM,
Such soft errors can be prevented.
第4図は、本発明の他の適用対象としての
ECL(エミツタ・カツプルド・ロジツク)型式
のバイポーラ・ダイナミツクRAMのメモリセル
構造を等価回路で示したものである。図示のメモ
リセルは、マルチエミツタトランジスタQ1,Q2
及び抵抗R1,R2でフリツプフロツプを構成した
もので、VCCは電位源、ADはアドレス線、D,
はそれぞれデータ線を示す。このようなメモリ
セル構造を有するバイポーラRAMにおいても、
特に大容量・高集積度のものにおいては、α線照
射により生じた電子−ホールペアが容易にフリツ
プフロツプの状態を反転させ、ソフト・エラーを
ひき起こす。 FIG. 4 shows another application target of the present invention.
This is an equivalent circuit diagram of the memory cell structure of an ECL (emitter coupled logic) type bipolar dynamic RAM. The illustrated memory cells are multi-emitter transistors Q 1 , Q 2
and resistors R 1 and R 2 constitute a flip-flop, where V CC is a potential source, AD is an address line, D,
indicate data lines, respectively. Even in bipolar RAM with such a memory cell structure,
Particularly in large-capacity, highly integrated devices, electron-hole pairs generated by alpha ray irradiation easily reverse the state of the flip-flop, causing soft errors.
このようなソフト・エラーも前述のMOS型
RAMの場合と同様に本発明の適用により効果的
に防止することができるものである。 This kind of soft error is also the same as the MOS type mentioned above.
Similar to the case of RAM, this can be effectively prevented by applying the present invention.
第1図は、本発明の一実施例による半導体装置
を示す断面図、第2図は、本発明の適用対象であ
るMOS型RAMのメモリセル構造を示す基板断面
図、第3図は、第2図のメモリセルの等価回路
図、第4図は、本発明の他の適用対象としてのバ
イポーラ型RAMのメモリセル構造を示す等価回
路図である。
10・・絶縁性ベース、11,18・・封止ガ
ラス層、14・・半導体チツプ、16・・α線遮
蔽層、17・・絶縁性キヤツプ。
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a substrate showing a memory cell structure of a MOS RAM to which the present invention is applied, and FIG. FIG. 2 is an equivalent circuit diagram of the memory cell, and FIG. 4 is an equivalent circuit diagram showing the memory cell structure of a bipolar RAM to which the present invention is applied. 10: Insulating base, 11, 18: Sealing glass layer, 14: Semiconductor chip, 16: α-ray shielding layer, 17: Insulating cap.
Claims (1)
といたシリコン又は石英の高純度材料の粒子から
なる絶縁物層を被着したことを特徴とする半導体
装置。1. A semiconductor device characterized in that an insulating layer made of particles of a high-purity silicon or quartz material bound with a binder is deposited on the surface of an active region of a semiconductor chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3547879A JPS55128850A (en) | 1979-03-28 | 1979-03-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3547879A JPS55128850A (en) | 1979-03-28 | 1979-03-28 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55128850A JPS55128850A (en) | 1980-10-06 |
JPS627700B2 true JPS627700B2 (en) | 1987-02-18 |
Family
ID=12442865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3547879A Granted JPS55128850A (en) | 1979-03-28 | 1979-03-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55128850A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55140253A (en) * | 1979-04-18 | 1980-11-01 | Fujitsu Ltd | Semiconductor device |
JPS57195151A (en) * | 1981-05-27 | 1982-11-30 | Denki Kagaku Kogyo Kk | Low-radioactive resin composition |
-
1979
- 1979-03-28 JP JP3547879A patent/JPS55128850A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS55128850A (en) | 1980-10-06 |
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