JPS6286852A - Laminated structure type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a laminated structure type semiconductor device which can stably operate by forming an insulated gate transistor that source and drain potentials are not secured on a circuit configuration in a semiconductor substrate. CONSTITUTION:In a laminated structure type semiconductor device, polycrystalline silicon layers 19, 20 are used as the source and drain electrodes of wiring materials of an MOS transistor formed in a semiconductor substrate 11 of the first layer, polycrystalline silicon layers 21, 22 are used as gate electrodes of MOS transistors of the first and second layers. MOS transistors in which source and drain potentials are not secured to a predetermined potential in the circuit configuration are formed in the substrate 11 of the lowermost layer, back electrodes 31 are formed on the substrate 11, and the substrate potential is applied from here to secure the substrate potential. Thus, it can prevent an erroneous operation due to a bipolar operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a stacked structure semiconductor device in which a specific element is formed within a semiconductor substrate as the lowest layer.

[Technical Background of the Invention II] In recent years, stacked structure semiconductor devices have attracted attention as a method for increasing the capacity of semiconductor elements. With conventional structures in which elements are mounted two-dimensionally, that is, two-dimensionally, on a semiconductor substrate, it is difficult to increase the degree of integration because the mounting density is determined by the processing standards of the elements. However, since a stacked structure semiconductor device can be constructed by stacking elements, the packaging density can be easily increased by the amount of stacking.

A simple structure of such a stacked structure type semiconductor device is shown in the sectional view of FIG. This semiconductor device has a two-layer structure, and one MOS transistor is formed in each of the first layer and the 211th layer. 11 is a semiconductor substrate, 1
2 to 18 are oxide films, 19 to 22 are polycrystalline silicon layers, 23 and 24, and 25 and 26 are diffusion regions for the source and drain of MOS transistors, respectively. 27 is a single crystal layer deposited on the semiconductor substrate 11. Each of the second semiconductor layers 28 to 30 is a metal N pole made of aluminum.

The above polycrystalline silicon li! 19 and 20 are respectively used as source and drain electrodes or wiring materials of a MOS transistor formed in the first layer semiconductor substrate 11, and polycrystalline silicon layers 21 and 22 are used as the first layer and 2W1.
It is used as the gate electrode of each MOS transistor. The reason for using the polycrystalline silicon layer as the electrode and wiring material here is that the high m (
This is because low melting point metals such as aluminum cannot be used because there is a heat treatment step (at least 950° C.), for example a diffusion step.

The second layer semiconductor [127 is M
After forming an OS transistor, polycrystalline silicon is deposited thereon and is made into a single crystal by annealing, for example, by electron beam irradiation. In addition,
The element isolation of the 1st layer and the 2H layer uses a generally known oxide film isolation such as LOGO8.The above diffusion layers 23 and 24 and 25 and 26 are used to form an n-channel or n-channel MOS transistor. According to n
It is formed by diffusing p-type impurities or p-type impurities.

[Problems with Background Art] In the above structure, a potential can be applied to the first layer substrate 11 from the back surface, but the second layer semiconductor! 1
21 is surrounded by an insulating film, so it is difficult to apply a potential to it. For this reason, the following disadvantages occur in conventional stacked structure semiconductor devices. For example, 2WJ
When a static random access memory (referred to as SRAM) is formed on the semiconductor @27, if a potential is not applied to the semiconductor @27 that serves as the substrate, a malfunction may occur in which the data in the memory cell is lost. do.

This will be explained with reference to the circuit diagram of the SRAM shown in FIG. One memory cell 40 is an n-channel M
It is composed of a general 0MO8 (complementary MO8) flip-flop 45 composed of OS transistors 41 and 42 and n-channel MOS transistors 43 and 44, respectively, and transfer gates 46 and 47 composed of n-channel MOS transistors. Let's take a 6-transistor type as an example. Here, when the substrate potential of each transistor is in a floating state, that is, when no potential is applied to the substrate, the source potential of the n-channel transistors 41 and 42 constituting the flip 70 tube 45 is V.
The power supply potential of the DD is set to the ground potential of Vss in the n-channel transistors 43 and 44. For this reason, in these transistors, the substrate (back gate)
The potential is VDD - VF for an n-channel transistor.
(Vp is the forward voltage of the pn junction), and in an n-channel transistor, it is stable at VF.

However, in the transfer gates 46 and 47, the source
Since the drain potential fluctuates, the substrate potential also fluctuates in accordance with the potential fluctuation. For example, when the data stored in one memory cell 40 is at the "1" level and the node 48 of this memory cell 40 is at the "1" level (Van), the word line 50 connected to the transfer gate 46 is selected. Then, the drain of the transfer gate 46, that is, the potential of the bit line 51 becomes a high potential that is lower than Vno by the threshold voltage of the transistor 46. At this time, the substrate potential of the transfer gate 46 also becomes a high potential, and its value becomes approximately equal to vDDIR. Next, consider the case where data is written to another memory cell 53. When attempting to write "O" level data into another memory cell 53, one bit line 51 is set to "O" level (Vas potential) and the other bit line 52 is set to "1".
level (Voo potential). At this time, the word line 50 is set to the "0" level, and the transfer gates 46 and 4γ in the memory cell 40 are turned off. On the other hand, the word line 54 is set to the "1n level" and the memory cell 54 is set to the "1n level".
Transfer gate 3 is on. By doing this, "0" level data is written into the memory cell 53. At this time, the transfer gate 46 of the memory cell 40 is affected by the parasitic n-type as shown in FIG.
A pn type bipolar transistor 60 is formed, and the substrate potential of this transfer gate 46 is high as described above. Therefore, when the potential of the bit line 51 drops, the emitter potential of the parasitic bipolar transistor 60 is brought to approximately the ground potential, and the transistor 60
starts bipolar operation. As a result, a current flows from the collector, drawing out the charge at the node 48. In other words, the potential of node 48 decreases. When the bipolar operation reaches the saturation region, the potential of node 48 drops to near the ground potential. Therefore, the n-channel MOS transistor 43 in the memory cell 40 is turned off, and conversely, since the bit line 52 is at a high potential, the memory cell 40
The potential of node 49 within the memory cell 40 increases, and the data stored in memory cell 40 is inverted. As described above, there arises a problem that the contents of non-selected memory cells are destroyed when data is written.

The above-mentioned malfunction mode is not limited to SRAM, but also applies to a single cell, a selection MOS transistor 73 whose gate is connected to a word line 71 and a drain connected to a bit line 72, and data storage, as shown in FIG. A dynamic random access circuit consisting of a capacitor 74 for
The same can be said of memory (hereinafter referred to as DRAM).

Furthermore, this is a problem that occurs in general circuits in which the drain and source potentials are not fixed at predetermined potentials due to the circuit configuration.

[Purpose of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to provide a stable structure by devising the arrangement of elements so as to prevent malfunctions in a stacked structure semiconductor device. An object of the present invention is to provide a stacked structure type semiconductor device that can be operated.

[Summary of the Invention J To achieve the above object, the present invention includes stacking at least one semiconductor layer on a semiconductor substrate with an interlayer insulating layer interposed therebetween, and forming layers within the semiconductor substrate and each of the semiconductor layers, respectively. In a stacked structure semiconductor device configured to form an element, an insulated gate transistor whose source and drain potentials are not fixed due to the circuit configuration is formed within the semiconductor substrate. When this semiconductor device is a static random access memory, a transformer 71 gate is formed in the semiconductor substrate, and when this semiconductor device is a dynamic random access memory, a memory cell transistor is formed in the semiconductor substrate. It is formed within the base.

[Embodiments of the Invention] Next, the present invention will be described in detail. In the stacked structure semiconductor device of the present invention, as described above, the source or drain potential is not fixed at a predetermined potential due to the circuit configuration.
As in the device shown in FIG. 1, which has a structure similar to that shown in FIG. It is. Alternatively, a contact may be provided at a desired location on the surface of the substrate 11, and the substrate potential may be applied from there.

By applying a desired potential to the substrate 11 in this manner, the substrate potential can be fixed.

Therefore, malfunctions due to bipolar operation that occur in conventional devices can be prevented.

Roughly speaking, if the device shown in FIG. 1 is an SRAM, the transfer gates (46 and 47 in FIG. 3) are connected to the bottom layer of the substrate 1.
1, and a drive transistor (43 and 44 in FIG. 3) and a load transistor (43 and 44 in FIG.
By configuring the memory cells in a stacked structure such as 41 and 42) in FIG. 3, the area occupied by the memory cells can be reduced and the degree of integration can be improved. This eliminates the need to apply a substrate potential to the semiconductor H27 in the upper layer,
This is because there is no need to have a complicated structure.

If the device shown in FIG. 1 is a DRAM, the cell transistor (73 in FIG. 5) is placed in the substrate 11 at the bottom layer, and a capacitor (14 in FIG. 5) is placed in the semiconductor layer 27 above it.
), the degree of integration can be improved for the same reason as the SRAM described above.

Also, since the source of the transistor 73 (meaning the connection node between the transistor and the capacitor) is on the bottom layer,
There is also the effect that radiation such as alpha rays does not reach the diffusion layer, suppressing the occurrence of soft errors.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a stacked structure type semiconductor device that can perform stable operation by devising the arrangement of elements.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the configuration of an apparatus according to an embodiment of the present invention;
FIG. 2 is a sectional view showing the configuration of a conventional device, FIG. 3 is a circuit diagram of a general memory, and FIGS. 4 and 5 are circuit diagrams for explaining the conventional device. 11... Semiconductor substrate, 12-18... Oxide film, 19
~22... Polycrystalline silicon layer, 23.24.25.2
6... Diffusion region, 27... Second semiconductor layer, 28
~30... Metal electrode, 31... Back electrode. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5

Claims (3)

[Claims] (1) In a stacked structure semiconductor device in which at least one semiconductor layer is stacked on a semiconductor substrate via an interlayer insulating layer, and elements are formed in the semiconductor substrate and in each of the semiconductor layers, a source and 1. A stacked structure semiconductor device, characterized in that an insulated gate transistor whose drain potential is not fixed due to circuit configuration is formed within the semiconductor substrate. (2) The insulated gate transistor is static
The stacked structure semiconductor device according to claim 1, which is a transfer gate of a random access memory. (3) The stacked structure semiconductor device according to claim 1, wherein the insulated gate transistor is a memory cell transistor of a dynamic random access memory in which a memory cell is constituted by a memory cell transistor and a capacitor.