JPH0582983B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor memory element having a three-dimensional active layer stacked structure, which reduces the memory capacity per unit area without increasing the chip area. This technology improves device access time to more than double the speed of conventional devices, reduces delays through vertical wiring between layers using through-holes, and can be achieved with almost the same amount of effort as conventional device design. The present invention relates to a semiconductor memory element having an element structure.

<Prior Art> In recent years, efforts have been made to speed up the access time of semiconductor memory elements. However, improvements in device characteristics are highly dependent on advances in process technology, and new technology development is always required. On the other hand, speed-up based on conventional process technology currently involves using two or more memory elements and adding a circuit to control these memory elements from the outside, thereby more than doubling the access time of semiconductor memory elements. A method to increase the speed to (interleaving method)
is taken. An outline of this configuration is shown in FIG. Here, 1 includes a circuit for distributing address signals to two storage elements and an address register. Reference numeral 2 denotes a chip selection control unit that selects a memory element based on the distributed address input.
3 and 4 are semiconductor memory elements, DRAM,
These include SRAM, EEPROM, EPROM, and mask ROM. Reference numeral 5 denotes a data control unit, which includes a circuit that distributes data during writing or reading to two storage elements, a data register, and a circuit that selectively combines data from the two storage elements.

<Problems to be Solved by the Invention> In this method, two or more semiconductor memory elements and a control section are added, so even if 1, 2, and 5 were combined into one chip, the configuration would be three or more chips. . Further, if each chip is made into one chip, the chip size becomes large or the storage capacity is reduced.

In view of the above points, the present invention has been developed to more than double the access time of a conventional memory element without reducing its storage capacity or increasing its chip area, and to reduce the amount of effort required for design compared to conventional memory elements. The purpose of this invention is to provide a semiconductor memory element with a three-dimensional active layer stack structure that can be realized with approximately the same amount of labor as required for one element.

<Means for Solving the Problems> In order to achieve the above object, the semiconductor memory element of the present invention is an interleaved type semiconductor memory element, and includes a first active layer in which memory cell arrays each having the same pattern are formed, and A second active layer is stacked, and the bit line arrays of the two memory cell arrays are placed between the first active layer and the second active layer via an insulating film to recrystallize the polycrystalline silicon by beam irradiation. The active layer is formed in a third active layer of an SOI structure formed using a single-crystal silicon substrate, and each of the active layers is electrically connected via a through hole. In addition to the layers, polycrystalline silicon is recrystallized by beam irradiation on top of the insulating layer, and the active layer is made of a three-dimensional SOI (Silicon On Insulator) structure with a laminated structure, with some additions to the circuit. By simply making modifications, a single chip semiconductor memory element can be provided that has approximately the same chip size, the same storage capacity, and can be accessed at more than twice the speed as a conventional two-dimensionally realized semiconductor memory element.

<Examples> Examples of the present invention will be described below with reference to the drawings.

The principle of the present invention is the same as described above when using two or more semiconductor memory elements and controlling the input and output of each. As shown in FIG. 2, when two memory elements are used, the access speed can be doubled at most. First, in the case of reading, an address is input from ADR _IN shown in FIG. The address data entered in memory plane 1 is distributed in order to input the address data to the decoders of the two memory planes. For example, the address data at the first address goes to the address input of memory 3, the address data at the second address goes to the address input of memory 4, or vice versa. The th address data may be distributed to the address input of the memory 3. In this way, the address data input from ADR _IN is sequentially distributed to address inputs of three and four memories. However, since 1 has a register, the allocated address data is held for the necessary time until the output is determined. In this way, the address data input to each memory plane has been input for the time required for conventional memory to access at this point, and looking at the memories 3 and 4 themselves, It provides access at the highest speed achieved by conventional memory. From the data output from the memories 3 and 4, a data control section 5 takes out the finalized data in the order of address input and outputs it from D _OUT . The same applies to writing, but the difference from reading is that 5 requires an operation to allocate the write data and an operation to hold the allocated data in a register. Here, the time for which data is held may be the minimum time required for each memory 3, 4 for writing. In the case of writing, each of the memories 3 and 4 operates at the fastest access time of a conventional semiconductor memory element.

To specifically illustrate the above explanation, timing charts for reading and writing are shown in Figures 3 and 4.
As shown in the figure. FIG. 3 shows the case of reading and is shown in comparison with a conventional semiconductor memory element. (a) shows reading from a conventional memory, and (b) shows reading from a memory according to the present invention. FIG. 4 shows the case of writing, and similarly to FIG. 3, it is shown in comparison with a conventional semiconductor memory element. (a) shows writing in the conventional memory, and (b) shows writing in the memory of the present invention. As shown in Figures 3 and 4, both ADR _IN , D _OUT and ADR _IN , D _IN
Focusing on this, in the case of the present invention, the number of times of reading and writing within the same time is twice as many as in the conventional case. In other words, if two layers of memory planes are used, the access speed can be up to twice as high, and if three layers are used, the access speed can be up to three times faster. However, individual memories are operating at the same speed as traditional access times.
In other words, for both reading and writing,
A _3IN , D _3OUT , A _4IN , D _4OUT and A _3IN , D _3IN , A _4IN ,
_D4IN operates with the same access time as conventional memory.

In the present invention, based on the above principle, three-dimensional SOI
As an example of a stacked structure of active layers, a double interleave type memory is cited as one of the semiconductor memory elements in which three active layers are stacked. FIG. 1 is a schematic diagram of its structure. The first active layer 21 is a single crystal silicon substrate, and all transistors are
The second active layer 22 is formed by NMOSFET, and after forming a circuit pattern such as NMOSFET and wiring on the first active layer 21, an insulating layer is formed, and polycrystalline silicon is formed by beam irradiation in an SOI structure on top of the insulating layer. The active layer formed by recrystallization forms a PMOSFET. A circuit pattern is formed on the second active layer 22, and a third active layer 23 is formed with an SOI structure in the same way as the second active layer is formed on top of the second active layer with an insulating layer interposed therebetween. Lays out and forms circuit patterns such as wiring. 1st
The connections between the active layer and the second active layer and the connections between the second and third active layers are vertically wired using through holes. 6 and 7 are memory cell arrays (memory planes) each composed of NMOSFETs. 8 runs the bit line arrays of memory planes 6 and 7. 9, 9', 9'' are address input buffers, which are formed across the first, second, and third active layers. 10, 10', and 10'' are data input/output buffers. The active layer is also formed across three layers. The input and output buffers are common to both memory planes 6 and 7. Row decoders 11 and 11' are formed of first and second active layers, and are row decoders of the memory plane 7. Similarly,
14 and 14' are also row decoders, which are formed of the second and third active layers, and are row decoders of the memory plane 6. Column decoders 12 and 12' are formed of the first and second active layers, and are connected to the memory plane 7.
It is a column decoder for Similarly, 15,1
5' is a column decoder for the memory plane 6 formed by the second and third active layers. 13,1
3' selects the address data for the memory plane 7 formed by the first and second active layers, and inputs the address data to the decoder for the memory plane 7 until the output data is determined or This is an address register for holding the time until input data is written into the memory cell of the corresponding address. Similarly, 16 and 16' are address registers for the memory plane 6, which are formed by the second and third active layers. Sense amplifiers (buffers) 17 and 17' for the memory plane 7 are formed of first and second active layers. Similarly, 1
Reference numerals 8 and 18' designate sense amplifiers (buffers) for the memory plane 6, which are formed of second and third active layers. 19, 19', 19'' are control signal generation units for address input control to sequentially distribute address data from 9, 9', 9'', and data input/output control related to data input or data output during writing and reading. and is formed over the first, second, and third active layers. 20, 20',
20'' is a data input/output control unit for sequentially connecting data output from each memory plane in order of addresses, or distributing data input for writing to each memory plane in order of corresponding addresses; It is formed over three active layers: second and third.

As mentioned above, 6 and 7 memory arrays are
Although it is formed of NMOSFET, other peripheral circuits are formed of the first and second active layers, the second and third active layers, or the first, second and third active layers and a vertically structured stack type. It is made of CMOS. 6,7
The memory array is also one channel of N channel.
Although it is formed of transistors, the bit line is not placed in the same active layer as each memory array, and the memory cells are also formed vertically and small.

FIG. 5 shows an equivalent block diagram of a double interleaved memory chip according to an embodiment of the present invention formed in this manner. There is an address input buffer 31 for receiving address input, which corresponds to 9, 9', 9'' in FIG. 33 and 34, the input/output control signal generation circuit outputs an address input control signal to the address register for distributing the address to the decoders for memory arrays #1 and #2, and the address is The input/output control signal generation circuit 32 is sequentially distributed and held in the address registers 33 and 34.
19'', and #1 address register 33 is 1.
3, 13', #2 address register 34 is 16,
It corresponds to 16'. The distributed address data enters the row decoders 35 and 37 of #1 and #2 and the column decoders 36 and 38 of #1 and #2, respectively, and the data corresponding to each address is sent to #1 and #2, respectively.
Read from #2 memory array 39, 40,
#1, #2 sense amplifier (buffer) 41, 4
Send to 2. Each output data is input to the output control 431 of the data input/output control circuit 43, and data #1 and #2 are connected in the order in which the address inputs are distributed and sent to the data input/output buffer 44. Then, an output corresponding to each address is obtained. During writing, address inputs are similarly distributed sequentially and input to the decoders of each memory plane. Also,
Unlike when reading, write data corresponding to an address is also distributed to each memory plane. In this case, the write data passes through the input section of the input/output buffer 44 and passes through the data input/output control circuit 43.
In the input control 432, data registers 433 and 434 of #1 and #2 branch according to the address, are held until the writing is confirmed, and are written to each memory plane at the corresponding address through the sense amplifier (buffer). It can be done. #1 row decoder 35 is 11, 11' in FIG. 1, #2 row decoder 37 is 14, 14', #1 column decoder 36 is 12, 12', #2 column decoder 38 is 15, 15', # #1 memory array consists of 7 and 8 bit line arrays, and #2 memory array 40 consists of 6 and 8 bit line arrays. #1
Sense amplifier (buffer) 41 is 17, 17',
#2 sense amplifier (batshua) 42 is 18,1
It is 8'. The data input/output control circuit 43 is 20,
20', 20'', the data input/output buffer 44 is 1
Corresponds to 0, 10', 10''.

In this way, it has two layers of the same memory plane, and the peripheral circuit is a stacked CMOS.For #1, the first and second active layers are used, and for #2, the second and third active layers are used. , #2, the first part is common to #2.
It is commonly formed in the second and third active layers.

It is easy to realize a multiplexing system that further advances the duplex interleaving of this embodiment by laminating the necessary active layer on the three-layer laminated structure.

<Effects of the Invention> As described above, the semiconductor memory element of the present invention includes a first active layer formed on a single-crystal silicon substrate and an insulating layer that electrically insulates the first active layer. A three-dimensional structure semiconductor memory element having a second active layer obtained by melting and growing polycrystalline silicon by irradiation, and a laminated structure of a plurality of active layers, in which a memory plane is formed in two or more layers. By simply adding an input/output control circuit, it is possible to achieve memory access speeds more than twice as fast as conventional chips with approximately the same area. Furthermore, in one embodiment of the present invention, the memory cell array is formed with one channel of NMOS, but the bit lines are not run on the same active layer but are separated, and the peripheral circuits are also formed with stacked CMOS. Since the memory cells and each element themselves are also reduced in size and vertical wiring is performed using through holes, efficient wiring with short lengths is realized, and wiring delays are also reduced. Furthermore, since it has a stacked structure, #1 memory formed by the first and second active layers and #2 memory formed by the second and third active layers can be formed using the same mask pattern. , the conventional mask layout work for one semiconductor memory element and the mask layout work for the input/output control section is all that is required, and the rest can be realized by CAD processing using mask layers and coordinate transformation, and the number of masks can be reduced to the size of the three-dimensional active layer. Although this increases due to the layered structure, it can be realized with the same amount of work as designing conventional semiconductor memory elements, and data conversion during CAD work is sufficient, reducing errors in mask layout. Compared to the conventional two-dimensional process of combining two chips and the control section into one chip, this reduces the amount of work, improves reliability, and shortens the design period.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a double interleaved memory according to an embodiment of the present invention. FIG. 2 is a conceptual diagram showing the principle of the present invention using two conventional semiconductor memory elements and adding an input/output control section to them. FIGS. 3 and 4 are diagrams showing read and write timing charts of a semiconductor memory element according to the present invention in comparison with a conventional semiconductor memory element. FIG. 5 is an equivalent functional block diagram of a double interleaved memory according to an embodiment of the present invention. Explanation of symbols, 21...first active layer, 22...
second active layer, 23... third active layer;

Claims (1)

[Claims] 1. An interleaved semiconductor memory device, in which a first active layer and a second active layer each having a memory array of the same pattern are stacked, and the bit line of the two memory arrays is stacked. The row is
is formed in a third active layer of an SOI structure formed by recrystallizing polycrystalline silicon by beam irradiation between the first active layer and the second active layer with an insulating film interposed therebetween; A semiconductor memory element characterized in that active layers are electrically connected via through holes.