JPS6083366A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6083366A JPS6083366A JP58191513A JP19151383A JPS6083366A JP S6083366 A JPS6083366 A JP S6083366A JP 58191513 A JP58191513 A JP 58191513A JP 19151383 A JP19151383 A JP 19151383A JP S6083366 A JPS6083366 A JP S6083366A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- resistor
- gate electrode
- layer
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は・α線による誤動作を改良した半導体記憶装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which malfunctions caused by alpha rays are improved.
周知の如く、半導体記憶装置例えばスタティックＲＡＭ
（ＳＲＡＭ ）は、第１図に示す等価回路を有してい
る。図中のＱｌ、Ｑ２は、夫々一方のドレイン領域を他
方のダート電極に接続したＭＯＳ トランジスタでアシ
、該トランジスタＱ＋。As is well known, semiconductor memory devices such as static RAM
(SRAM) has an equivalent circuit shown in FIG. Ql and Q2 in the figure are MOS transistors each having one drain region connected to the other dirt electrode, and the transistor Q+.
Ｑ２の夫々の負荷側には抵抗” １ ＋ Ｒ２が接続さ
れ、フリップフロッゾ回路を構成している。A resistor "1 + R2 is connected to each load side of Q2, forming a flip-flop circuit.
前記トランジスタＱｌ 、Ｑｚのンース領域は夫々接地
されている。前記フリッゾフロップ回路の各メモリ・ノ
ードＮ、、Ｎ、は、Ｍｏ８ ）ラン９ｘりＱａ ｌ Ｑ
４ を介して４’１ ＋ Ｊ２のビット線ＢＬ、ＢＬに
接続されている。前記ＭＯ８）ランリスタＱｓ、Ｑ４は
、メモリセルが選択され書き込み、読み出しが行なわれ
る際にはＯＮ状態となって前記ビット線ＢＬ、ＢＬとフ
リッゾ回路との情報の伝達が行なわれる。同ＭＯ８）ラ
ンリスタＱ＋１１Ｑ４のダート電極は夫々飴１９４ＷＬ
、ＷＬに接続されている。The ground regions of the transistors Ql and Qz are respectively grounded. Each memory node N, , N, of the frizzo flop circuit is connected to the run 9x Qa l Q
It is connected to the bit lines BL and BL of 4'1+J2 via 4'1. The MO8) run listers Qs and Q4 are turned on when a memory cell is selected and data is written or read, and information is transmitted between the bit lines BL and the frizzo circuit. Same MO8) The dart electrode of Lanlista Q+11Q4 is 194WL each.
, connected to WL.
こう：した構造のＳ ＲＡＭとしては、従来第２図及び
第３図に示す構造のものが知られている。As an SRAM having such a structure, the structures shown in FIGS. 2 and 3 are conventionally known.
図中□め１，２（斜線部分）ｌｉＭＯ８）ランリスタＱ
＋、Ｑ＊ の夫々のダート電極を、３（斜線部分）はＭ
ｏ８ ）ランリスタＱｓＨＱ＜の共通のダート電極を夫
々示す。これらｒ ）電極１〜３及び語線（ＷＬ）４は
、夫々ｎ型のＳｉ基板５上のＰフェル６上に夫々絶［１
１７ｔ−介して形成された第１の多結晶シリコン層から
形成されてい）回路のノードＮ２となるｎ＋層８．第１
．第２のビット線（Ｂ Ｌ 、 Ｂ Ｌ）９．．９２と
接続されるｎ＋廟１０．ｖｌ！ｌｓ端子と接続するｎ＋
層１１が夫々形成されている。前記ダート電極１〜３の
一部を含むＰウェル６上には、絶縁膜１２を介して前記
ｎ＋層８及びＭＯＳトランジスリスｌ、Ｑａのダート電
極１，２と夫々接続する第２の多結晶シリコン層からな
る抵抗（Ｒ，、Ｒ２）ＪＪ、１４が形成されている。な
お、この抵抗１３．１４は第２図においては点々部分を
示す。こうした構造のＳ ＲＡＭにおいて、従来、第１
図中のダート抵抗Ｒｇは＃？！は零でちる。□ in the figure 1, 2 (hatched area) liMO8) Run lister Q
+, Q* dart electrodes, 3 (hatched area) is M
o8) Common dart electrodes of run lister QsHQ< are shown respectively. These r) electrodes 1 to 3 and word lines (WL) 4 are disposed on a P-fer 6 on an n-type Si substrate 5, respectively.
17t- layer formed from the first polycrystalline silicon layer formed through the n+ layer 8. which becomes the node N2 of the circuit. 1st
．． Second bit line (B L , B L)9. ．． 92 and connected to n+ temple 10. vl! n+ connected to ls terminal
Layers 11 are formed respectively. On the P well 6 including a part of the dirt electrodes 1 to 3, there is a second polycrystalline layer connected to the n+ layer 8 and the dirt electrodes 1 and 2 of the MOS transistors L and Qa through an insulating film 12, respectively. A resistor (R,, R2) JJ, 14 made of a silicon layer is formed. Note that the resistors 13 and 14 are shown as dotted portions in FIG. In an SRAM with this structure, conventionally, the first
Is the dirt resistance Rg in the diagram #? ! is zero.
しかしながら、従来のＳ ＲＡＭによれば、例えハＭＯ
８）ランリスタＱ１の１層８にα線が入射されると、Ｐ
ウェル６及びｓｉ基板５に電子−正孔対が発生しその中
電子が前記ｎ１Ｂ８に収集される。この結果、１層８が
たとえ高電位でおる場合にもｎ＋層８の電位が下がシ、
誤動作を引き起こす、いわゆるソフトエラーが生じる。However, according to the conventional SRAM, even if
8) When α rays are incident on the first layer 8 of the runlister Q1, P
Electron-hole pairs are generated in the well 6 and the Si substrate 5, and the electrons are collected in the n1B8. As a result, even if the first layer 8 is at a high potential, the potential of the n+ layer 8 is lowered.
So-called soft errors occur that cause malfunctions.
こう、したことから、前記ダート抵抗Ｒ１＋Ｒ２を１０
にΩ以上にすることによりソフトエラーを防止する技術
が知られている（、 １９８３． ｓｙｍｐｏａｉ ｕ
ｍｏｎ ＶＬＳＬ ｔｅｃｈｎｏｌｏｇｙ ” ＣＲ１
ｓｑｌａｔｅｄｃｅｌｌ ｆｏｒｓｏｆｔ ｅｒｒｏｒ
ｐｒｅｖｅｎｔｉｏｎ ’ Ｔ、ηｚｕＱ＆Ｔ、 ５
ａｋｕｒａ１）。かかる技術に↓シ、ダートのキャパシ
タンスＣｇとダート抵抗、〜に与る時定数ＣｇＲｇによ
ってたとえｎ＋層８の接合部分の電位が下がろうとも、
第４図に示すＱｑ ＜ Ｍｏ１ｌ ）ランリスタＱ１の
ダート電極１の電位、、の低下を阻止できる。なお、同
図において、（ａ）１：はメモリが初期″Ｈ”を記憶し
ているノード（Ｍｏ８ トランジスタＱ１のダート電極
）を、（ｂ）は、メモリが初期”Ｈ’を記憶しているノ
ード（、、Ｎｚ接合電位）を、（Ｃ）はメモリが初期＠
Ｌ＃を記憶しているノード（Ｍｏ８ ）ランリスタＱ１
のゲート電極）を、（ｄ）はメモリが初期” Ｌ”を記
憶しているノード（Ｎ２接合電位）を夫々示す。しかる
に、従来、ダート抵抗Ｒｇは、第２図におい、、てＭｏ
８ ）ランリスタＱｌ、Ｑ２のダート電極１，２用の第
２の多結晶シリコン層を全面に高抵抗にし、ダートの分
布定数型の抵抗を使う事が考えられていた。Based on this, the dirt resistance R1+R2 is set to 10
A technique is known to prevent soft errors by setting the resistance to Ω or more (1983. sympoai u
mon VLSL technology ”CR1
sqlatedcell forsoft error
prevention 'T, ηzuQ&T, 5
akura1). With this technology, even if the potential at the junction of the n+ layer 8 decreases due to the dart capacitance Cg, the dart resistance, and the time constant CgRg,
It is possible to prevent a decrease in the potential of the dirt electrode 1 of the run lister Q1 (Qq < Mo1l) shown in FIG. 4. In the same figure, (a) 1: indicates the node (dart electrode of Mo8 transistor Q1) where the memory stores the initial "H", and (b) indicates the node where the memory stores the initial "H". node (,, Nz junction potential), (C) is the initial state of the memory @
Node storing L# (Mo8) Run lister Q1
(d) shows the node (N2 junction potential) at which the memory initially stores "L". However, conventionally, the dirt resistance Rg is
8) It has been considered to make the second polycrystalline silicon layer for dart electrodes 1 and 2 of runlisters Ql and Q2 high in resistance over the entire surface, and to use distributed constant type resistance of darts.
従って、ダート分布定数型ＱＣＲ時定数を使うため、ダ
ート抵抗ＲｇのノードＮ １ ｒ Ｎ ２ に近い部盆
ではＮｌ ＋ Ｎ ２の電位の動きに追従して効果的で
ない。具体的に述べれば、例えばノードＮｌが”Ｈ”か
ら“Ｌ’にな、るとＭｏ８）ランリスタＱ２のダートも
一部同じ速度でＨ″からＬ”になシ、ＭＯＳトランジス
リスｚは一部ＯＦＦとなる。これは、ノードＮ２の電位
を＠Ｌ＃にしておくコンダクタンスを減少せしめ、誤動
作の方向に近づける。これによ、シ、分布型のＣＲ時定
数ではあまり効果的でない・
〔発明の目的〕
本発明は上記事情に鑑みてなされたもので、ンフ、トエ
ラーを阻止し得る半導体記憶装置を提供することを目的
とするもので、必る。Therefore, since the dart distributed constant type QCR time constant is used, it is not effective in the basin near the node N 1 r N 2 of the dart resistance Rg because it follows the movement of the potential of Nl + N 2. To be more specific, for example, when the node Nl changes from "H" to "L", part of the dart of the run lister Q2 changes from "H" to "L" at the same speed, and part of the MOS transistor z changes from "H" to "L" at the same speed. OFF.This reduces the conductance that keeps the potential of node N2 at @L# and approaches the direction of malfunction.This causes the distributed CR time constant to be less effective. Purpose] The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device that can prevent errors.
本発明は、半導体基体の表面に拡散層を設け、同基体上
に絶縁膜を介してダート電極及び該ダ−ト電極、拡散層
に夫々接続する抵抗を設け、前記ダート電極、抵抗の接
触部分に高抵抗層を設けることによって、効果的々ｃ
、ｎ時定数をメモリ・セルに導入し、もってソフトエラ
ーを阻止することを図ったことを骨子とする。The present invention provides a diffusion layer on the surface of a semiconductor substrate, a dirt electrode and a resistor connected to the dirt electrode and the diffusion layer, respectively, through an insulating film on the substrate, and a contact portion between the dirt electrode and the resistor. By providing a high resistance layer on the
, n time constants are introduced into memory cells to prevent soft errors.
以下、本発明の一実施例を第５図を参照して説明する。 Hereinafter, one embodiment of the present invention will be described with reference to FIG.
なお、第１図〜第仝図の従Ｉ Ｓ ＲＡＭと同部材のも
のは同符号を付して説明を省略し、要点のみを説明する
。Components that are the same as those of the sub-IS RAM shown in FIGS. 1 to 2 are given the same reference numerals, and the explanation thereof will be omitted, and only the main points will be explained.
図中の２１は、フリツノフロ、ノ回路を構成スル一方の
ＭＯＳ ）ランリスタＱ＋ のゲート電極１の抵抗１３
との接触部分表面に形成された高抵抗層としての薄い酸
化膜である。この酸化膜２１はダート電極１を薄く酸化
することによって形成され、１０にΩ以上のコンタクト
抵抗（Ｒｇ）を有する。なお、他方のＭＯＳトランジス
リス２についても同様に酸化膜が形成されている。21 in the figure is a resistor 13 of the gate electrode 1 of the MOS transistor Q+, which constitutes the circuit.
This is a thin oxide film that serves as a high resistance layer formed on the surface of the contact area. This oxide film 21 is formed by thinly oxidizing the dirt electrode 1, and has a contact resistance (Rg) of 10Ω or more. Note that an oxide film is similarly formed on the other MOS transistor 2.
しかして、本発明によれば、ＭＯＳトランジスリス ！
＋ Ｑ ！のダート電極１，２と抵抗（Ｒ１゜Ｒ２）１
３．１４との接触部分に１０にΩ以上の抵抗Ｒｇ’！ｚ
有する薄い酸化膜２１が設けられているため、メモリセ
ルを構成するＭＯＳ）ランリスタＱｌ、Ｑ２ のダート
電極１，２を、α線による電荷を受けとめるジャンクシ
ョン（ノー）’Ｎ。Therefore, according to the present invention, MOS transistors!
＋Q! Dart electrodes 1, 2 and resistance (R1°R2) 1
3. Resistance Rg' of 10Ω or more at the contact part with 14! z
Since the thin oxide film 21 is provided, the dirt electrodes 1 and 2 of the MOS (MOS) run listers Ql and Q2 constituting the memory cell are connected to junctions (NO)'N that receive charges caused by α rays.
又はＮ２ ）からＣＲ時定数によって完全に分離する童
ができ、ソフトエラーを防止できる。これは、ジャンク
ションに収集されるα線による電流の大部分が０．２ｎ
ｓ程度の短いノ４ルスであｐｌこれ以上の長いＣＲ時定
数を有しているダート電極にはこの効果は波及しないこ
とに基づく。(or N2) can be completely separated by the CR time constant, and soft errors can be prevented. This means that most of the current due to α rays collected at the junction is 0.2n
This is based on the fact that this effect does not spread to the dart electrode, which has a CR time constant as short as s and a longer CR time constant than pl.
なお、前述したコンタクト抵抗ＲｇをｌＯｋΩ以上とし
た理由について、第６図を参照して説明する。第６図に
おいて、横軸はＲｇを、縦軸は■α−ｍｉｎを示す。こ
のＩα−ｍいは、これ以上のα線による電流が流れると
エラーとなる。ｉ、；小の電流値である。また、普通Ｃ
ｊ＝１０ｆぐらいである。同図よシ、Ｒｇ ＞Ｒｇ−ｃ
ｒｉｔ （臨界抵抗）の領域ＡではＩα１．ｎ＝ωとな
シ、どんなにα線による電流が大きくてもエラーを発生
しないことが確認できる。そして’ Ｒｇ−ｃｒｉｔは
通常十数にΩでオシ、この抵抗以上では効果的にソフト
エラーを防止できることが明らかでちる。ただし、Ｒｇ
がある程度であればソフトエラーに対して効果があるた
め、抵抗の制限性についてはおまシ問題とならない。The reason why the above-mentioned contact resistance Rg is set to 1OkΩ or more will be explained with reference to FIG. 6. In FIG. 6, the horizontal axis represents Rg, and the vertical axis represents ■α-min. If a current of more than this Iα-m flows due to α rays, an error will occur. i,; is a small current value. Also, normal C
It is approximately j=10f. Same figure, Rg > Rg-c
In region A of rit (critical resistance), Iα1. When n=ω, it can be confirmed that no error occurs no matter how large the current due to α rays is. And, 'Rg-crit' is normally set to more than 10 ohms, and it is clear that soft errors can be effectively prevented when this resistance is exceeded. However, Rg
If it is to a certain extent, it is effective against soft errors, so the restrictiveness of the resistance is not a problem at all.
なお、上記実施例では、高抵抗層としての薄い酸化膜を
ダート電極の表面を薄く酸化することによって形成する
場合について述べたが、これに限らない。例えば、ダー
ト電極の抵抗と接触すべき部分に酸素をイオン注入する
ことによって形成してもよいし、あるいは抵抗を形成す
るための材料を低抵抗するイオン注入時に該材料の底面
までイオン到達しないようにすることによって形成して
もよい。In the above embodiment, a case has been described in which a thin oxide film as a high resistance layer is formed by thinly oxidizing the surface of a dirt electrode, but the present invention is not limited to this. For example, it may be formed by ion-implanting oxygen into the part of the dirt electrode that should be in contact with the resistance, or when ions are implanted into a material for forming the resistance to have a low resistance, the ions may be formed so that they do not reach the bottom of the material. It may also be formed by
また、上記実施例では半導体糸体としてＳｉ基板を用い
たが、これに限らず、例えばサファイア等の絶縁性基板
上に半導体層を形成したものを用いてもよい。Further, in the above embodiment, a Si substrate was used as the semiconductor thread, but the present invention is not limited to this, and a structure in which a semiconductor layer is formed on an insulating substrate such as sapphire may also be used.
以上詳述した如く本発明性によれば、ソフトエラーを阻
止した信頼性の高いＳ ＲＡＭ等の半導体記憶装置を提
供できるものである。As detailed above, according to the present invention, it is possible to provide a highly reliable semiconductor memory device such as an SRAM that prevents soft errors.
第１図は従来のＳ ＲＡＭの等価回路図、第２図は第１
図図示のＳ ＲＡＭの平面図、第３図は第２図のＸ−Ｘ
線に沿う断面図、第４図は従来の改良したＳ ＲＡＭに
よるＣＲ分離セルの電圧波形を示す特性図、第５図は本
発明の一実施例に係るＳ ＲＡＭの断面図、第６図はコ
ンタクト抵抗と電流の関係を示す特性図である。
１〜３・・・ダート電極、４・・・語録（ＷＬ）、５・
−・ｎ型のＳｉ基板、６・・・Ｐウェル、７，１２・・
絶縁膜、８ 、１０ 、１１− ｎ＋層、１３ 、７４
−抵抗、２ノ・・・薄い酸化膜（高抵抗層）。
出願人代理人 弁理士 鈴 江 武 彦第１Ｆ！Ｉ
第２図
ＩｊＬ Ｂ（−Figure 1 is an equivalent circuit diagram of a conventional SRAM, and Figure 2 is an equivalent circuit diagram of a conventional SRAM.
A plan view of the S RAM shown in the figure, Figure 3 is taken along line X-X in Figure 2.
4 is a characteristic diagram showing the voltage waveform of a CR separation cell in a conventional improved S RAM, FIG. 5 is a sectional view of an S RAM according to an embodiment of the present invention, and FIG. 6 is a sectional view taken along the line. FIG. 3 is a characteristic diagram showing the relationship between contact resistance and current. 1-3... Dirt electrode, 4... Vocabulary (WL), 5.
-・N-type Si substrate, 6...P well, 7, 12...
Insulating film, 8, 10, 11- n+ layer, 13, 74
-Resistance, No. 2...Thin oxide film (high resistance layer). Applicant's representative Patent attorney Takehiko Suzue 1st floor! I Fig. 2 IjL B(-
Claims (5)
カップルした２個のＭＯＳ ）ランジスタニヨり情報を
記憶する半導体記憶装置において、半導体基体と、この
基体の表面に設けられた拡散層と、同基体上に絶縁膜を
介して設けられたケ゛−ト電極及び該ゲート電極、□拡
散層に夫々接続する抵抗と、前記ダート電極、抵抗の接
触部分に設けられた高抵抗層とを具備する１ことを特徴
とする半導体記憶装置。(1) In addition to having a high resistance load, it also has dirt resistance,
A semiconductor memory device that stores information using two coupled MOS) transistors includes a semiconductor substrate, a diffusion layer provided on the surface of this substrate, and a gate electrode provided on the substrate with an insulating film interposed therebetween. A semiconductor memory device comprising: a resistor connected to the gate electrode and the diffusion layer, respectively; and a high resistance layer provided at a contact portion of the dirt electrode and the resistor.
・とによって形成されることを特徴とする特許請求□の
範囲第１項記載の半導体記憶装置。(2) The semiconductor memory device according to claim 1, wherein the high resistance layer is formed by oxidizing the surface of the dirt electrode.
部分に酸素をイオン注入することによって形成□される
ことを特徴とする特『「Ｂ１“ｊ求の範囲第１項記載の
半導体記憶装置０(3) The semiconductor according to item 1, characterized in that the high resistance layer is formed by ion-implanting oxygen into a portion of the dart electrode that is to be in contact with the resistance. storage device 0
抗するイオン注入時に該材料の底面までイオンが到達し
ないようにする仁メにょシ形成されることを特徴とする
特許請求の範囲第１項記載の半導体記憶装置。(4) Claims characterized in that the high-resistance layer is formed in a layer that prevents ions from reaching the bottom surface of the material used to form the resistor when ions are implanted to reduce the resistance of the material. 2. The semiconductor memory device according to item 1.
徴とする特許請求の範囲第１項記載の半導体記憶装置。(5) The semiconductor memory device according to claim 1, wherein the high resistance layer has a resistance of 10Ω or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191513A JPS6083366A (en) | 1983-10-13 | 1983-10-13 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191513A JPS6083366A (en) | 1983-10-13 | 1983-10-13 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6083366A true JPS6083366A (en) | 1985-05-11 |
| JPS6141143B2 JPS6141143B2 (en) | 1986-09-12 |
Family
ID=16275902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58191513A Granted JPS6083366A (en) | 1983-10-13 | 1983-10-13 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6083366A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6992916B2 (en) * | 2003-06-13 | 2006-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
| US7486541B2 (en) | 2003-06-13 | 2009-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistive cell structure for reducing soft error rate |
-
1983
- 1983-10-13 JP JP58191513A patent/JPS6083366A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6992916B2 (en) * | 2003-06-13 | 2006-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
| US7486541B2 (en) | 2003-06-13 | 2009-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistive cell structure for reducing soft error rate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6141143B2 (en) | 1986-09-12 |
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