JPH0115959B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to MOS type RAM (Random Access Memory), and more particularly to non-volatile static RAM incorporating integrated floating gate circuitry.

Many static RAMs store binary data (1
and 0), a bistable semiconductor circuit such as a flip-flop is used as the memory cell. In such static memory cells that store information, the current from the power supply is 2
It flows continuously into one of the two intersectingly connected branches and not into the other branch. Two (binary) distinct memory states are provided for storing information by the conducting and non-conducting states of its branches. Therefore, such semiconductor memory cells can be considered volatile because if power is removed, the current that distinguishes memory states will no longer flow in the branches and the information in the cell will be lost. be. Such volatility is a drawback of conventional semiconductor memories, and circuit elements and structures have been developed that provide non-volatility to semiconductor circuits when power is removed. An example of this is the 1978 IEEE Inter−
national Solid State Circuits Conference
Digest, 108-109p, E. Harari et al., “256-bit Non-Volatile Static RAM”; 1978, IEEE
International Solid State Circuits Conference
Digest 196−197p, “E ² −” by F. Berenga et al.
PROM TV Synthesizer”; 1978, IEEE
Trans. Electron Devices Vol. ED−25, No.8,
1061−1065p, “Military standard grade 1024-bit non-volatile semiconductor RAM” by M. Horne et al.; 1978, IEEE
Trans. Electron Devices, Vol. ED−25, No. 8,
1065−1070p, “1K non-volatile semiconductor read/write RAM” by Y. Uchida et al.; 1971, IEEE
International Solid State Circuits Conference
Digest, 80-81p, D. Frohmann's "A Fully-
Decoded2048 Bit Electrically
Programmable MOS-ROM”; U.S. Patent No.
No. 3660819; U.S. Patent No. 4099196; U.S. Patent No.
No. 3500142; Applied Phys. of Dimaria et al., 1975.
“Interface Effects and
High Conductivity in Oxides Grown from
RM of 1977
Anderson et al., J. of Appl. Phys., Vol. 48, No. 11,
4834−4836p, “Evidence for Surface Asperity
Mechanism of Conductivity in Oxide Grown
on Polycrystalline Silicon" etc.

Devices based on MOS floating gate structures have traditionally been used to extend data storage time. A floating gate is an island of conductive material electrically isolated from, but capacitively coupled to, a substrate, forming the gate of a MOS transistor. Depending on whether or not there is charge on this floating gate, the MOS transistor is made conductive (ON) or non-conductive (OFF), and the binary data "1" or "1" corresponding to the presence or absence of this floating gate charge is It forms the basis as a memory that stores “0”. Various methods are known for injecting and removing signal charges from floating gates. Once a charge is applied to the gate, it is permanently stored. This is because the floating gate is completely surrounded by insulating material, which acts as a barrier for discharge from the floating gate. Charge is introduced into the floating gate using hot electron injection and/or tunneling mechanisms, exposed to radiation (UV, X-rays), and removed from the floating gate by avalanche injection or tunneling. Ru. The term tunneling is used here in a broad sense, including the emission of electrons from the surface of a conductor into a nearby insulator across an energy barrier.

Nonvolatile static RAM memories incorporating floating gate nonvolatile devices that utilize very thin gate oxides are well known, but they also have a number of drawbacks. Charges float through a relatively thin (50–200 Å) oxide film.
Passing in both directions from and to the gate device, the oxide film is difficult to fabricate with the required integrity. Because of the bidirectional nature of its very thin tunnel oxide, non-volatile RAM cells have problems with disturbances that can cause memory contents to be lost. Such problems, among other things, result in limitations on the number of read cycles and disturbances of a cell's memory contents caused by adjacent cell operations. Other non-volatile RAM devices do not use floating gates but instead use metal/nitride layers.
Using an oxide/semiconductor structure, charge is retained at the interface between silicon nitride and silicon oxide. but,
Such MNOS devices have interference problems that limit not only read cycles but also write cycles, preventing widespread use of MNOS devices.

It is desirable to interface non-volatile elements with RAM circuitry to provide non-volatility to semiconductor memory arrays. However, known interfaced devices have various drawbacks. For example, such an interface can be achieved by introducing a conductivity imbalance caused directly by the non-volatile elements between two branches of intersecting static RAM cells. However, such conductivity imbalances result in DC offset currents in cross-coupled static RAM cells that must be removed when the cells are in normal RAM mode operation, and Such unbalance provides read and write disturbance margin for the entire memory circuit. Additionally, such margins limit manufacturing and pose problems with inspection.

Other important factors for interfacing non-volatile elements to static RAM cells are compactness and device design simplicity, which influence circuit size and cost. Known interfaces require complex interfaces in terms of control signals and external transistors;
The result is a large non-volatile static RAM circuit, which increases cost accordingly.

Each known non-volatile static RAM device also has the disadvantage of requiring high operating currents and voltages. These needs create practical limitations in device power, speed, and complex circuit design. Well-known non-volatile statistics
RAM devices also utilize semiconductor substrates as the main element for programming non-volatile memory elements and for storing data in non-volatile elements.
Since a high voltage is applied to the RAM power supply line, it is difficult to separate the RAM cell design and manufacturing process from the nonvolatile element design and manufacturing process and perform independent optimization. Furthermore, the data in the non-volatile storage element
When called into a RAM cell, the data is stored in RAM
The same is true when it is added complementary to a cell, or vice versa, when it is first written to a non-volatile element. Thus, when a binary "0" is written to a non-volatile element, represented by the first branch of a conventional flip-flop RAM cell being conductive and the second branch being non-conductive, ,
When the data is then written back to the RAM cell, the first branch of the RAM cell will be non-conductive and the second branch will be conductive, representing a binary "1". Such complementary calls, which are not direct, true calls, must be handled by external circuitry or compensated for by the user of the memory, which is very inconvenient.

Accordingly, it is an object of the present invention to provide an improved non-volatile static RAM cell and memory device. Another object of the invention is to provide electrically conductive or DC balanced as well as static
It is an object of the present invention to provide a non-volatile static RAM device and a memory array that can provide a static RAM cell with capacitive or dynamic imbalance in the interface relationship between the RAM cell and the non-volatile element. Another object of the present invention is to provide a non-volatile static RAM part and a non-volatile part of a memory cell that can be optimized by separating them.
Its purpose is to provide RAM cells and devices. Another object of the present invention is to provide a compact, high density non-volatile static RAM that is relatively simple and inexpensive to manufacture.
It is to provide cells. Yet another object of the present invention is to provide a nonvolatile static RAM that draws little DC current from a high voltage source during programming.

Broadly speaking, the present invention provides one of two memory states.
a volatile semiconductor bistable memory cell for storing binary data as one memory cell; an addressing device for reading and writing binary data from the memory cell; and a storage state of the volatile memory cell. a nonvolatile semiconductor memory device that stores binary data as one of two charge levels on a floating gate, regardless of the charge level of the floating gate. Additionally, the apparatus capacitively couples the volatile memory cell to the floating gate memory element and bistablely couples the volatile memory cell to the floating gate memory element as a predetermined floating gate memory state.
an apparatus for copying a memory state of a memory cell to a floating gate element, and capacitively coupling the floating gate element to a volatile semiconductor memory cell, when the volatile memory cell is powered; and an apparatus for copying a memory state of a floating gate of a non-volatile element to a volatile cell.
An apparatus for copying the memory state of a bistable memory cell to a floating gate element and an apparatus for copying the memory state of a floating gate element to a bistable memory cell transfer the initial memory state of a bistable cell to a floating gate element. Teing・
When copying to a gate device and subsequently copying the memory state of the floating gate device to a non-volatile cell,
The bistable cell operates to return to its initial memory state. Bistable volatile memory cells are preferably static MOS transistors.
or a cross-coupled flip-flop circuit element consisting of six transistors, the device according to the invention is configured in a memory array like a RAM array in a conventional manner. Additionally, the non-volatile memory cells may be constructed from dynamic memory cells.

The present invention will be described in detail below with reference to Examples.

An embodiment of a non-volatile static RAM cell according to the present invention is shown in FIGS. 1-5. RAM
Cell 10 also includes a volatile static bistable flip-flop memory cell 12 and a non-volatile electrically programmable floating gate device 14. Cell 10 is X-Y
Because they form part of an address RAM, volatile memory cells 12 will be referred to hereinafter as static RAM cells, although they may be used in other memory configurations.

FIG. 1 is a top view of a nearly scaled chip circuit illustrating the polycrystalline silicon electrode structure of device 10. FIG. The circuitry of device 10 is shown in FIG. 5, although the circuit elements of device 10 of FIG. 1 are shown in a more simplified form than in FIGS. 2-4 to clearly describe the invention. As shown in Figure 1,
Cell 10 layout design is approximately 82.5 microns x 79 microns (measured on a 5 micron scale)
It is relatively compact and can be used as a unit in a random access array of continuous cells.

In Figure 2, silicon substrate 1
The region of 1 n implantation is defined by a solid line with diagonal lines. Additionally, to illustrate each polycrystalline layer of the stacked structure of device 10, the next polycrystalline layer is displayed with a different line type. The pattern of the first polycrystalline layer 50 is shown as a dotted solid line, and the pattern of the second polycrystalline layer 5
2 is shown as a solid line with an x, and the third polycrystalline layer 54 is shown as a dashed line. The "buried contact" region where polycrystalline layer 54 contacts the n-channel region is shown in fine dotted lines. In Figures 1 and 2, the area of contact with the metal is indicated by a square with an cross.

Static RAM cell 12 shown in FIG.
The random access array in which it is constructed may generally be of conventional design.
RAM cells 12 are connected to store lines 100 of metal wires that carry power and signals across the array (FIG. 2) connected to each cell, indicated by crossed lines;
V _ss potential line 102, V _cc potential line 104,
Y data line 106 and complementary Y data line 108 are read and written by appropriately addressing and sensing current conditions in accordance with well known methods. In the example cell 10, the _Vss potential is about 0 volts, the _Vcc potential is about 5 volts, and the substrate potential _Vbb is about -
It is 3 volts.

The static RAM cell 12 is dynamically or capacitively unbalanced coupled to a nonvolatile floating gate 14 and, upon operator command,
The current memory contents of volatile static RAM cell 12 are stored in non-volatile elements. The capacitive coupling means also allows the contents of the non-volatile floating gate device 14 to be read out to the volatile static RAM cell device 12 when desired by operation of appropriate circuit elements. The memory contents of the static RAM cell 12 and the non-volatile element 14 are independent of each other except at the time of a specific transfer command. In particular, RAM cell 1
The current memory contents of 0 are not stored in the non-volatile memory element 14 whenever the RAM cell 12 is written by the cell addressing and writing device, and the memory contents of the static RAM cell are " The data is only stored in the nonvolatile element 14 by the operation of the capacitive transfer circuit when a "store" command is issued. Actually, non-volatile memory element 1
4 is a programmable "shadow" for the device 10.
ROM”.

As shown in FIG.
It includes a transistor static RAM cell 12 and a non-volatile electrically rewritable floating gate memory element 14. The floating gate memory device 14 is a non-volatile storage method and device (Japanese Patent Application Laid-Open No. 1983-99780) filed on the same day.
detailed in.

The critical elements of the non-volatile memory cell components of the device are of opposite conductivity type to the substrate and are electrically isolated located within the substrate at the surface of the substrate in close proximity to the floating gate. bias electrode. The bias electrodes are separated by an oxide film.
It is also possible to place it in the area under a portion of the storage electrode, in which case floating
Located under both the gate and erase/storage electrodes. Since the bias electrode is of the opposite conductivity type as the substrate, it is
It is electrically isolated from the substrate by means of insulating the pn junction and the bias electrodes to be supplied to the device. The main functions of the bias electrode are to inject charge into the floating gate (i.e. write cycle) and to drain charge (i.e.
During the erase cycle, the floating gate is capacitively biased properly.

The bias electrode potential is set when the transistor turns
It is controlled by a switching element or device such as a transistor in the substrate that connects the bias electrode to a predetermined reference voltage source when turned on. When a switching element (e.g., a switching transistor) is off, the bias electrode is made sufficiently positive with respect to the program electrode below the floating gate, so that charge passes from the program electrode to the floating gate, and then a relatively large The floating gate potential is changed in turn by making it negative. This negative change in floating gate potential due to charge injection is sensed by suitable sensing means such as a MOS transistor. Similarly, the erase/storage electrode, which at least partially overlaps but is insulated from the floating gate, is brought to a predetermined positive potential so that charge passes from the floating gate to the erase/storage electrode.
In this manner the floating gate is brought to a relatively high positive potential, which is sensed by suitable means such as a sense transistor.

An automatic self-adjusting compensation circuit of the memory device is formed in the region under the matching of the floating gate, the bias electrode, and the substrate, and the write operation when charge is flowing from the program gate to the floating gate. During the process, the current pulse to the floating gate is shaped. This circuit is characterized by unevenness of the program gate and floating
Minimize stress on the tunnel oxide film between the gate and the gate. However, after many operating cycles, higher stress is required to write to the floating gate due to the charge trapped in the oxide. This circuit automatically adjusts this condition by providing additional stress when needed. The combination of providing minimal stress to the floating gate, current pulse shaping, and providing extra stress compensates for the trapped charge, which is a key factor in extending the effective cycle number of the device according to the invention. Furthermore, by taking advantage of the semiconductor electrical properties of the bias electrode and its placement on the surface of the substrate semiconductor, this circuit can be made very small. In this respect, when electrically isolated,
The bias electrode transfers the potential of most of the erase/storage electrode to the floating gate.
It acts as a variable capacitive coupling device that couples capacitively as a function of the gate. In this regard, capacitive coupling of the erase/storage electrode potential to the floating gate increases the potential between the floating gate and the program electrode sufficiently to transfer charge from the program electrode to the floating gate. used for. However, the capacitance of a capacitive coupling device is such that a portion of the erase/storage electrode potential coupled to the floating gate is floating.
It changes so that it decreases as the potential of the gate decreases, in other words, it decreases as the potential difference between the bias electrode and the floating gate increases. Therefore, charge transfer from the program electrode to the floating gate reduces capacitive coupling, which in turn reduces charge transfer to the floating gate.

As shown, the cell structure of device 10 is constructed on a monocrystalline p-type silicon wafer substrate 11, which substrate is doped in the range of approximately 1 x 10 ¹⁴ to 1 x 10 ¹⁶ atoms per cubic centimeter. has an acceptor. An electrically insulated polysilicon floating gate 2 is provided in close proximity to the substrate and is capacitively coupled to a bias electrode 7 in the substrate 11. Bias electrode 7 is formed in substrate 11 of the conductivity type opposite to that of substrate 11 and has a donor impurity concentration in the range of about 1×10 ¹⁷ atoms/cm ³ in the exemplary embodiment. The bias electrode 7 can be formed by conventional techniques such as diffusion or ion implantation, and in the illustrated embodiment is formed with a thickness of approximately 1 micron and an implant concentration of 1×10 ¹² to 1×10 ¹⁵ per cm ² . Ru.

The variable capacitance of an electrode with respect to the depletion region is expressed as a function of the potential difference between the electrode and the substrate (1970, Bell Systems
Technical Journal, 49, 587−593p, Boyle &
Smith’s “Charge Coupled Semicon-ductor”
In the illustrated embodiment, the variable capacitance CC2 of the floating gate 2 with respect to the bias electrode 7 is expressed as follows.

where C _O is the maximum capacitance per cm ² of the capacitor formed by the adjacent surface of floating gate 2, and is expressed as: C _O = ε/X and B = qK _S NX/Kd It is.

Here, ε is the dielectric constant of the silicon dioxide region 5 between the floating gate 2 and the bias electrode 7.

X is the thickness of the dielectric region between floating gate 2 and bias electrode 7.

q is the electric charge, _K is the relative permittivity of silicon, K is the relative permittivity of the region 5 separating _the bias electrode 7 and the floating gate 2, N is the doping concentration of the bias electrode 7,
ΔV is the value obtained by subtracting the potential V _FG of the floating gate 2 from the potential V _N+ of the bias electrode 7, and is slightly larger than zero, and V _FB is the flat band voltage.

Therefore, CC2 is approximately equal to C _O (constant) at very high doping concentrations N, and is almost zero at very low doping concentrations N (assuming other parameters are constant). The capacitance CO2 thus becomes smaller as the floating gate 2 becomes more negative in receiving electrons. However, when ΔV is less than zero, capacitance CC2 has a relatively constant maximum value C _O.

Variable capacitance CC2 is floating
The voltage coupling the gate 2 to the bias electrode 7 is controlled so that the potential difference between the program electrode and the floating gate drives the tunneling current, which is effectively controlled by controlling the doping concentration of the bias electrode.

The illustrated RAM cell 12 includes two cross-coupled static inverter circuits that combine to form a static 6-transistor flip-flop memory element in conventional MOS RAM.
Consists of design. In this regard, the RAM memory elements 12 each have a depletion pull-up
data node 29 to transistors 31 and 32;
It consists of cross-coupled flip-flop transistors 27, 28 connected via 30. Flip-flop transistor 27,2
8 is connected to the ground terminal 24, and depletion pull-up transistors 31 and 32 are connected to the ground terminal 24.
RAM Connected to power supply terminal _Vcc . Array ("row" or "word") "X" select transistors 33, 34 are similarly connected to data nodes 29, 30 for array selection throughout the memory array of which device 10 forms a part. be done. Selection of cell 12 in the cell array is accomplished by applying a _Vcc potential to the gate of one of the X address transistors 33, 34 and one of the Y ("column") address lines; are connected to complementary data output nodes 35, 36, thereby turning on the Connect to and.

Reading the addressed cell 12 is done by pulling both “bit” lines through a high resistance to the potential V _cc
This is done by holding the flip-flop
The state of the flop (1 of transistors 27 or 28)
(one on and the other off), current flows in either of the "bit" lines and reading is accomplished by sensing the differential current. cell 12
Writing to cell 12 is carried out in the same way as reading by holding one "bit" line at potential V _cc and bringing the other "bit" lines to substrate potential V _ss .
This is done in a known manner by addressing the .

Cell 12 is thus accessed via "word""X" transistors 33, 34 with data and complementary data appearing at Y node 35 and node 36. Conventional RAM read/write operations are performed via data nodes 35 and 36. A cross-coupled static flip-flop is connected to terminal 2 of cell 12 when the power supply V _cc is connected continuously to terminal 2 of cell 12.
6, transistors 27, 28, with complementary states appearing at nodes 29 and 30
31 and 32.

The structure of the static RAM cell 12 can be realized using well-known semiconductor processes and photolithography. Although one static RAM design is shown in the illustrated embodiment, other suitable designs may be used. For example, although transistors 31 and 32 are shown as depletion devices in example cell 10, in other embodiments these transistors may be replaced with suitable resistors.

As shown, the RAM cells are interfaced with non-volatile memory elements 14. The illustrated nonvolatile cell device 14 includes a floating gate and means for transferring electrons to and removing electrons from the floating gate. Cell device 14 further includes an automatic self-regulating circuit that increases the number of valid write cycles in non-volatile device 14. operatively, transferring electrons to the floating gate to place the floating gate in a relatively negative potential memory state; and removing electrons from the floating gate to place the floating gate in a relatively positive potential memory state; is the basis for memory storage in the non-volatile storage device 14. Charge transfer to and removal from the floating gate is accomplished by electron tunneling, which draws little DC current from the programmed high voltage source. The need for a small current from a high voltage source allows generation of this voltage "on-chip", which is clearly an advance over the prior art. Tunneling current is facilitated by the rugged islands present in the non-volatile element, and although a relatively thick oxide film separates the tunnel members of the cell, it is possible to reduce the tunneling current to the floating gate at an appropriate voltage. It is used for sufficient flow. Another characteristic of ruggedness is that it tends to cause tunneling current to flow predominantly in a single direction, and does not exhibit symmetrical current characteristics for reversed electric fields. This allows non-volatile device 14 to be relatively immune to loss of memory state due to premature and undesired discharge of charge due to read operations or adjacent cell operations. The operation of the illustrated nonvolatile memory device is controlled by the tunneling properties between polysilicon devices disposed on the substrate (including static RAM cells, which are largely controlled by phenomena within the substrate); RAM and non-volatile elements can be optimized independently. Therefore, this combination of static RAM cells and non-volatile elements can be easily applied to many other technologies.

When performing capacitive coupling, the node 29 of the RAM cell 12 is capacitively coupled to the nonvolatile element 14 via the capacitive circuit element 23 having a capacitance C1 and the transistor 8. Complement data node 30 similarly connects transistor 20
and a capacitive circuit element 1 having a capacitance C2.
7 capacitively coupled to non-volatile element 14 . Although various other circuit coupling elements will be described in detail below, it is important to note that static RAM cell 12 is only capacitively coupled to non-volatile element 14. Since no DC offset current load is applied to flip-flop data nodes 29 or 30 by interfacing with non-volatile device 14, static RAM cell 12
is almost balanced in steady state. This is a significant improvement over the prior art and leads to improved operating margins. The electrode and floating gate structure of device 10 is shown in FIG. 1, and FIG. 2 shows RAM cell 12 and non-volatile element 14.
A schematic structural diagram of the static system is shown, along with the relative size of each transistor and capacitive element.
Each component of RAM cell 12 and electrically rewritable non-volatile components of device 10 are shown.
FIGS. 3 and 4 show cross-sectional views taken from FIG. 2 and show generally "source-drain" connections with additional electrodes and metallization layers utilized to complete the device, in accordance with well-known processes and array designs. - A process in assembly called "doping" will be understood. The structure and operation of non-volatile device 14 is shown in the aforementioned patent application filed on the same date, and several additional devices forming an interface to static RAM cell 12 are disclosed. The non-volatile cell 14 of the preferred embodiment 10 utilizes three layers 50, 52, 54 of polysilicon in communication with various substrate elements and isolation dielectrics. Although the illustrated device 10 including non-volatile cells 14 is implemented in an n-channel MOS, other implementations and designs may be utilized.

The illustrated non-volatile device structure (FIGS. 2-4) is assembled on a p-type silicon substrate 11 and further includes a bias electrode of the opposite conductivity type as the substrate 11. Bias electrodes are introduced by well known techniques such as diffusion or ion implantation. A thermal oxide layer 4, which can be grown using known techniques to a thickness of about 12,000 angstroms, is provided for cell isolation purposes. The floating gate and non-volatile element electrodes are then etched and oxidized again to provide a thin oxide film 5, 6, which is then patterned (well known photolithography), etched and oxidized. The substrate is insulated from the polysilicon layer which is used to form program electrodes 1, floating gates 2, erase/storage electrodes 3 and other circuit elements and connecting leads. Thermal oxide layers 5, 6 separating the substrate from the polysilicon layer are grown to a thickness of about 1000 angstroms. The value of the substrate doping and the thickness of the oxide under the control gate of the various transistors, such as coupling capacitor 8, are selected to provide the desired threshold voltage according to well-known design techniques, and the The gate is formed from a polysilicon layer to match the cell design.

The first polysilicon layer is oxidized at about 1000° C. and the second polysilicon layer is similarly oxidized to provide irregularities 56 on the surface of these polysilicon layers, as shown by the serrations in FIGS. This is done through the process of The bumps formed under these conditions have an areal density of approximately 5 × 10 ⁹ per cm ² and an average base width of 456
angstrom, with an average height of 762 angstroms. This irregularity generates very high electric fields when relatively low voltages are applied between overlapping or adjacent polysilicon layers. When this asperity is negatively biased, it injects electrons into the relatively thick oxide films 42, 43 (800-1000 angstroms thick) even when relatively low voltages (e.g., 25 volts or less) are applied. This creates a sufficient electric field. When only one adjacent surface of the polysilicon layer has irregularities, a diode-like effect is provided. This is because electron tunneling is not enhanced from a flat surface when the asperities are relatively positively biased. The unevenness can occur in various states and is not limited to those described above. As shown, the polysilicon layers 50, 52, and 54 forming the electrodes and floating gate of device 10 are insulated from each other by a silicon oxide insulator. As shown in FIGS. 2, 3 and 4, the overlap region 18, 43 between the floating gate 2 and the program electrode 1 is
When a sufficient positive voltage is applied to the floating gate, the floating gate is removed from the program electrode.
This is the region where electrons pass through the isolation oxide film to the gate. Erase/memory gate 3 and floating
The overlap region between gates 2 is the region where electrons will pass from the floating gate through the isolation oxide when a sufficient positive voltage is applied to gate 3. The gate 3 overlaps the region 7, and the overlap area and the thickness of the insulating material 6,
A coupling capacitor 21 is formed with a capacitance CC3 determined by the potential difference of the erase/storage gate 3 with respect to the bias electrode 7 and the doping concentration of the bias electrode 7. Floating
The gate 2 also overlaps the bias electrode 7, and the overlap area, the thickness of the insulating material 5,
A coupling capacitor 22 is formed with a capacitance CC2 determined by the voltage of the floating gate 2 with respect to the bias electrode 7 and the doping concentration N. Region 9 is a standard heavily doped region that is typically formed during the processing steps that form the source and drain regions of each transistor. Capacitive element 25 having capacitance CE, capacitive element 1 having capacitance Csub
9, and a capacitive element 1 having a capacitance Cp.
8 is clearly shown in the drawing and can be understood from the various characteristics of the structural elements of the device 10. In this connection,
A split capacitor 23 of total capacitance C1 is formed between the first and third polysilicon layers. This capacitor plus the capacitance of the gate of transistor 8 connects node 29 to RAM cell 12 during a power-up cycle (including application of potential V _cc ) when transistor 20 is non-conducting.
The node 30 is started up more slowly than the node 30 of A capacitor 17 having a capacitance C2 is formed between the first polysilicon layer and the substrate region. The capacitance C2 and the gate capacitance of transistor 20 are equal to the capacitance C1
and the gate capacitance of transistor 8, causing node 30 to rise more slowly than node 29 during power-up. A capacitor 18 having a capacitance Cp is formed between the polysilicon floating gate of transistor 20 and the first polysilicon layer 50. This capacitor provides a structure for tunneling electrons from the program electrode 1 of the first polysilicon layer 50 to the floating gate 2. Tunneling occurs when a sufficiently large electric field is applied to capacitor 18 during "programming". An erase capacitor 25 having a capacitance CE is formed between the erase/storage electrode 3 and the floating gate 2 in the third polysilicon layer 54 . This capacitor 25 provides a structure for tunneling electrons from the floating gate 2 to the erase/storage electrode 3 ("erase"). Tunneling occurs when a sufficiently large electric field is applied to capacitor 25. Capacitor 25 couples the potential at the floating gate during programming. A capacitor 21 with a capacitance CC3 is formed between the erase/storage electrode 3 and the substrate n-implanted bias electrode 7. This capacitor is connected to capacitor 22 when transistor 8 is off.
provides a potential coupling to the floating gate 2 via. A capacitor 22 with a capacitance CC2 is formed between the floating gate 2 and the n-implanted substrate region of the bias electrode 7. When transistor 8 is non-conducting, a potential is coupled from erase/storage electrode 3 to bias electrode 7 (via capacitor 21) and then from bias electrode 7 to floating gate 2.
(capacitor 22). If a voltage is applied to electrode 3 when transistor 8 is conducting, bias electrode 7 is held at ground potential and capacitor 22 holds the floating gate at a low potential such that a large electric field is applied to capacitor 25.
It allows you to take. capacitance
Capacitor 19 with Csub is an undesirable parasitic p-n junction capacitor that decouples capacitors 22 and 21 from erase/storage electrode 3 during programming. This capacitor should be minimized. As shown, the transistor 8 is
It is a transistor that senses the state of the RAM cell 12 to mirror the memory state of the RAM cell and instructs the non-volatile element 14 to "program" or "erase" according to the memory state. transistor 20
is a transistor that transmits the state of the nonvolatile element 14 to the RAM cell 12. These capacitances, capacitors 21, 22, 17, and transistors 8, 20 will be explained in detail based on the description of cell operation.

By employing an n-channel silicon gate trilayer polysilicon fabrication process, a manufacturable, compact, and easy to operate non-volatile static RAM device 10 is provided as shown;
And it can be applied to, for example, a microcomputer. Memory device arrays can be used as power-down data storage capable (“crash-protected”) RAM or as non-volatile ROM.
It can be used as shared volatile RAM.
The cell can store two independent data bits, one in RAM section 12;
The other is stored in the non-volatile section 14 of each cell.

The RAM cell 12 operates independently from the ROM cell 14, and non-volatile memory is not necessarily a conventional RAM.
It is important not to share the "write" cycle. Instead, non-volatile storage occurs only when a "store" instruction is applied to the memory array. In the RAM array of device 10, the array can be used as a device for placing RAM data patterns onto corresponding non-volatile floating gate elements. In this regard, a corresponding non-volatile element portion of the array can act as an electrically rewritable read-only memory (ROM). The non-volatile element 14 will hereinafter be referred to as a ROM for ease of reference. Data is the future
Non-volatile to recall to RAM cell 12
Since this data storage can be stored in RAM element 14, this data storage can be performed in a full power down state or in a conventional
It may be desirable to operate on other conditions where RAM loses its data and cannot be recovered.

Furthermore, the RAM section 12 and ROM section 14 of the cell 10
is "transparent" so that the RAM section can operate almost independently of the data state of the ROM section. Because of this feature, and because the RAM section mirrors the true data state of the ROM section at power-up, the memory of device 10 when power is restored to the entire system is stored in a conventional mask-programmable ROM memory. - Any start program can be automatically loaded into the RAM array section of the array. Data or programs stored in ROM can be saved in corresponding RAM cells for indefinite recall. In operation of the device 10, the potential V _cc is applied to the RAM cell 12.
on-chip or off-chip when supplied with
By suitable control circuitry (not shown) on the chip, approximately
A single 25 volt "store" pulse is applied to the erase/storage electrode 3 to copy the memory contents of the RAM section 12 to the ROM section 14. power supply
Once removed from RAM cell 12, ROM 14 retains its data indefinitely, ie, until it is rewritten. Operating power supply V _cc becomes static again.
When added to RAM 12, data in ROM 14 is automatically and non-destructively copied. RAM like this
12 remembers where it "stopped" when power was removed, and more specifically remembers when the last 25 volt "store" command pulse occurred.

In operation, node 29 of bistable RAM cell 12 is in a high or low potential state, and node 30 is in a high or low potential state.
is in the opposite situation. The capacitive coupling device coupling the RAM cell 12 to the non-volatile element 14 is
In order to copy the memory state of RAM cell 12, RAM
The memory state of the cell 12 is sensed and a decision is made accordingly to inject or remove electrons from the floating gate 2. Here, when the node 29 is at a high potential, the transistor 8 is conductive, and the drain of the transistor is connected to the large reciprocal plate (n type) of the capacitors 21 and 22.
to ground. If about 25V “store”
When a pulse is applied to the erase/storage electrode 3, an electric field is applied to the capacitor 25 of sufficient magnitude to tunnel electrons from the floating gate 2 to the electrode 3. Floating gate 2 then becomes the gate of transistor 20. The entire circuit 10 is now "powered down" (all voltages removed),
Next, the RAM supply voltage V _cc backs up to about 5 volts.
Once loaded, the non-volatile element 14 is mapped to the RAM cell 12. Here, depletion load transistors 31 and 32 are connected to nodes 29 and 30.
try to raise each. However, transistor 20 is conducting (its gate is positively charged) and the capacitance of node 30 and the capacitance C2 of capacitor 17 and transistor 20
and the gate capacitance of node 29
is larger than the sum of the capacitance C1 of capacitor 23 and the gate capacitance of transistor 8, so node 30 is pulled up slower than node 29, and the cross-coupled amplifier becomes engaged when node 29 reaches about 1 volt. At the same time, node 29 is set to high level and node 30 is set to low level.

On the other hand, when the node 29 is initially at a low level, the transistor 8 is off (non-conducting) and the large n-reciprocal plates of the capacitors 21 and 22 of the bias electrode 7 are in a floating state. If the “store” of approximately 25 volts
When a pulse is applied to the erase/storage electrode 3, the capacitor 21 is potential coupled to the floating gate 2 via the capacitor 22. The 25 volt "store" voltage pulse is also coupled briefly to floating gate 2 via capacitor 25.
The effect is to generate an electric field in capacitor 18 large enough to tunnel electrons from program electrode 1 to floating gate 2, thereby charging the floating gate negatively. With the floating gate going negative, transistor 20 is turned off (non-conducting).

The entire circuit can then be powered down,
The _Vcc supply is then powered up. As mentioned above, transistors 31 and 32 are connected to node 2, respectively.
Trying to raise 9,30. However, in this case, the capacitance of node 29 and capacitor 2
The capacitance C1 of node 3 plus the gate capacitance of transistor 8 is greater than the capacitance of node 30 (transistor 20 is off). Therefore, node 30 will be slightly higher than node 29, thereby engaging the cross-coupled amplifier in the same manner as the previous store pulse command occurred to copy the RAM state to floating gate element 14. Set node 30 to high level and node 29 to low level.

Thus, in operation of device 10, RAM cell 12 is in a certain memory state (node 29 high and node 30 low, or node 29 low and node 30
(high), the ROM section 14 copies in such a way that the RAM cells 12 directly copy the same state back from the ROM section 14 upon power-up.

In order to recall data from non-volatile ROM cell 14 to RAM cell 12, the relationship of each capacitor must be satisfied when power supply _Vcc is powered up (again). In order to recall data from the ROM cell 14 to the RAM cell 12 when the transistor 20 is off, the capacitance C1 of the capacitor 23 and the transistor 8
The sum of the gate capacitance and the gate capacitance is sufficiently large,
Node 29 must always be pulled up later than node 30, sufficient to set node 29 of the cross-coupled amplifier of RAM cell 12 low (off) and node 30 high (on).

When transistor 20 is on, ROM cell 14
In order to recall data from to RAM cell 12, the sum of the capacitance C2 of capacitor 17 and the gate capacitance of transistor 20 is sufficiently larger than the sum of capacitance 21 of capacitor 23 and gate capacitance of transistor 8. It must be sufficient to set node 30 of the cross-coupled amplifier of RAM cell 12 low and node 29 high. The capacitances of these capacitors in the illustrated embodiment are:

Node 29 - approximately 0.10 picofarad Node 30 (transistor 20 on)
−about 0.20 picofarad Node 30 (transistor 20 is off)
- about 0.05 picofarads The aforementioned non-volatile static RAM cells are self-regulating and also have a compensation circuit in the non-volatile device which increases the number of effective uses in the non-volatile device as disclosed in the aforementioned same day patent application. It has certain advantages. Arrays of large numbers of such memory devices are easily formed on substrate chips with appropriate support circuitry and interconnected to provide non-volatile addressable static RAM memory devices. The data of the entire RAM array section corresponds to
It is easily copied to the ROM array section and is copied back to the RAM array when the RAM array is powered up.

Although the present invention has been described above based on the illustrated embodiments, it is clear that changes or additions can be made within the scope of the present invention.

The nonvolatile memory device of the present invention described above includes
It also has the following advantages. That is, at any time (copying data from the non-volatile memory means to the volatile memory cell) independently of and in no way affected by the state of the non-volatile data stored on the floating gate conductor (excluding during operation)
Volatile memory cells can also operate as random access memory (RAM) to which data can be read externally and externally written to. Furthermore, non-volatile memory means always safely store non-volatile data on the floating gate conductor, independent of and completely unaffected by the normal operation of the volatile memory cell as a RAM. I can do that. Thus, the nonvolatile memory device of the present invention has the freedom that the volatile memory cell and the nonvolatile memory means can operate independently.

Further, high current and high voltage for operation are not required.

[Brief explanation of drawings]

FIG. 1 is a top view of an embodiment of a non-volatile static random access memory cell according to the present invention, prior to metal contacts and interconnections. 2 is a top view of the non-volatile cell elements of the memory cell of FIG. 1; FIG. Figure 3 shows the second
3 is a cross-sectional view taken along line 3-3 of the non-volatile cell elements of the illustrated memory cell at an intermediate assembly stage; FIG. FIG. 4 is a cross-sectional view taken along line 4--4 of the non-volatile cell element of the memory cell of FIG. 2 at an intermediate assembly stage.
FIG. 5 is a circuit diagram of the non-volatile static random access memory cell of FIG. Symbol explanation, 1: Program electrode, 2: Floating gate, 3: Erase/storage electrode 3, 4,
5, 6: Oxide film, 7: Bias electrode, 10: Nonvolatile static RAM cell, 11: Substrate, 12: Volatile static RAM cell, 1
4: Nonvolatile element.

Claims (1)

[Claims] 1. A volatile semiconductor memory that stores binary data.
a cell, a means for reading from and writing to said volatile memory cell, and an insulated floating gate conductor for storing binary data at one of two different charge levels.
non-volatile memory means for storing the memory state of the bistable volatile memory cell therein as a bistable; means for transferring the floating gate conductor of the non-volatile memory means to the volatile memory cell with a predetermined one of the charge levels;
when power is applied to the volatile memory cell.
means for copying a memory state of a gate conductor to the volatile memory cell, the device comprising: means for copying a memory state of a gate conductor to the volatile memory cell; and a second state that creates an opposite capacitance imbalance between the data nodes, and when power is applied to the device, the floating
A non-volatile memory device comprising switching means for copying the current state of a gate conductor to said data node. 2. The nonvolatile memory device of claim 1, wherein said volatile memory cell is a bistable cross-coupled flip-flop memory cell. 3. The volatile memory cell has 6 transistors.
A non-volatile memory device according to claim 1, which is an n-channel static random access memory cell. 4. The volatile memory cell has 4 transistors.
A non-volatile memory device according to claim 1, which is an n-channel static random access memory cell. 5 The volatile memory cell has 6 transistors.
A non-volatile memory device according to claim 1, which is a CMOS/SOS static random access memory cell. 6. The non-volatile memory device of claim 1, wherein the non-volatile memory cell is a 6-transistor bulk CMOS static random access memory cell. 7. The nonvolatile memory device of claim 1, wherein said volatile memory cell is a dynamic memory cell. 8. The nonvolatile memory device of claim 1, wherein the nonvolatile memory means includes a plurality of electrodes, at least two of which and the floating gate conductor are comprised of three layers of polysilicon. memory device. 9. A non-volatile memory device according to claim 1, wherein irregularities are provided to facilitate electron flow to and from the floating gate conductor of the non-volatile memory means. 10 means for copying a memory state of said volatile memory cell onto said floating gate conductor includes an electrode in capacitive proximity to said floating gate conductor, said electrode having a "storage" voltage signal applied thereto; 2. A non-volatile memory device as claimed in claim 1, wherein the current memory state of said volatile memory cell is transferred to non-volatile memory means. 11. The non-volatile memory device of claim 1 comprising an integrated circuit array of similar cells. 12 The means for reading from and writing to said volatile memory cell comprises a single erase/storage gate capacitively coupled to said floating gate conductor, and a single positive polarity voltage is applied to said floating gate conductor. A non-volatile memory device according to claim 1, which allows both charging and discharging of the gate conductor.