KR830001767B1 - Non-Destructive Stop Isostatic Memory - Google Patents

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Description

Non-Destructive Stop Isostatic Memory

1 is a plan view of a non-destructive stationary constant speed call memory unit element according to the present invention in which metal contacts and interconnects are deposited on a known one.

FIG. 2 is a half plan view of non-destructive fragment elements of the memory elements illustrated in FIG.

3 is a cross-sectional view of the non-destructive segment element taken in line 3-3 of FIG.

4 is a cross-sectional view of the non-destructive fragment element taken at line 4-4 of FIG.

5 is a circuit diagram of a non-destructive stationary constant velocity call memory piece shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a randon access memory system (RAMS) made of metal-oxide-semiconductor (MOS), or MOS RAMS, and more particularly to a non-destructive stationary RAM system incorporating an integrated floating gate circuit. It is about.

Various stationary RMASs use bistable semiconductor circuits such as flip-flop circuits as storage pieces for binary data (1 and 0) measurement. In such static storage pieces for information storage, the current from the power supply must continue to flow in one of the two cross-coupled branch circuits and must not be in a different atmosphere.

Thus, two (binary) information accumulation applications impose distinct memory states according to the conductive and non-conductive branches. Therefore, if the power is dissipated, the semiconductor memory fragments are extinct because the information in the fragments is lost because the memory state that distinguishes the current stops moving in the current in the branch circuit. Since such extinction is a drawback in the conventional semiconductor memory system, considerable efforts have already been made to develop circuit elements and structures that can give endurance to semiconductor circuits even when power is lost. [E. Harari et al., "256-Bit Non-Destructive Static RAM," IEEE IEEE Solid State Circuit Digest, 1978, pp. 108-109: "E ² -PROM TV Synthesizer," IEEE Solid State Circuit International Conference, 1978. Digest, pp. 196-197: "Military 1024-Bit Non-Destructive Semiconductor RAM," IEEE Electronics Report ED-25, No. 8 (1978), pp. 1061-1065: Y. Yuhida et al., " Non-Destructive Read / Write RAM for 1K in Semiconductors ", IEEE Electronics Report, ED-25, No. 8 (1978), 1065-1070: D. Promann" Full Decoded 2048-Bit Electrical Programmable MOS " -ROM ", Digest International Conference of IEEE Solid-State Circuits, 1971 Page 80-81: U.S. Patent No. 3,660,819: U.S. Patent No. 4,099,196: U.S. Patent No.3,500,142: Dimera et al.," Conductivity of Oxides Grown in Polycrystalline Silicon Observation of Surface Protrusion Mechanisms "," Appl Phys "Journal, Vol. 48, No. 11 (1977), 48344836].

Devices based on the MOS floating gate structure have been conventionally used in systems for long term data storage. The floating gate is a group of conductors that is electrically insulated from the substrate but capacitively coupled to the substrate to form the gate of the MOS transistor. Depending on the presence or absence of charge in the floating gate, the MOS transistor becomes either conductive (ON) or non-conductive (OFF), so that the storage of the binary "1" or "0" data corresponding to the presence of charge on the floating gate. It is the basis of the device.

Various devices are shown for introducing and removing signal charge from a floating gate. Once the gate is charged, the charge is permanently trapped because the floating gate is completely surrounded by an insulating material that acts as a barrier to the discharge of the floating gate.

Charge can be introduced into the floating gate using high temperature electron injection or a tunneling mechanism. The charge can be removed from the floating gate by exposure to radiation (ultraviolet, X-ray) or by a tunneling effect. The term tunneling is used here in a wide range, including the electrons from the conductor plane being radiated across the energy barrier into the insulated dots.

Non-destructive stationary RAM memories are well known, which combines non-destructive elements of floating gates using extremely thin gate oxides, but these devices have several disadvantages. The charge enters and exits the floating gate in both directions through a relatively thin (50-200 μs) oxide, which is difficult to reliably manufacture with accurate dimensions. Due to the bi-directional nature of the ultrathin tunnel oxide, non-destructive RAM fragments can disrupt the problem of losing their accumulation.

In particular, these problems include a limitation on the number of read cycles, and confusion in three memory contents caused by the operation of adjacent three pieces.

Other non-destructive RAM devices do not use floating gates, but rather use a metal nitride-oxide semiconductor (MNOS) structure in which charge is preserved at the interface of silicon nitride and silicon dioxide. However, these MNOS devices are also limited to the wide use of MNOS devices because of their limitations in read cycles as well as read cycles.

It is necessary to connect the non-destructive element to the RAM circuit to give endurance to the semiconductor memory array. However, known connection devices have various disadvantages. For example, such a connection is achieved by obtaining an imbalance in conductance exhibited by a non-destructive element between two branches that are cross-coupled within the stationary RAM segment. However, this unbalanced conductance causes three cross-coupled static RAMs to have a DC compensation current, which must overcome this current when the three are in normal RAM operation, and this imbalance can confuse the read and write of the entire memory circuit. In addition, the manufacturing yield is limited and the test problem is exposed.

Another important factor in connecting non-destructive devices to static RAM segments is to provide density and simplicity in the device design, which affects the size and cost of the circuit.

However, the known connection system introduces complexity in control signals and unusual transistors, which is a reason for the large size of the non-destructive stationary RAM circuit and its high cost.

Many known non- destructive stationary RAM devices also suffer from the drawback of high current consumption and high voltage during operation. These conditions place practical limits on the power and speed of the device and on the complex circuit design. Similarly, various well-known non-destructive static RAM devices use a semiconductor substrate as a main element when programming non-destructive memory elements, which apply a high voltage to the RAM output line to accumulate non-destructive elements. It is difficult to optimize it independently from the non-destructive element design and assembly process.

Moreover, when the data contained in the non-destructive accumulator is recovered to the RAM fragments, the data is applied to the RAM fragments in the opposite state as originally written to the non-destructive components. Thus, if the binary "0" represented by the conductive first and nonconductive second branches in these conventional flip-flop RAM pieces is written to the non-destructive device and then written back to the RAM piece, then one of the three pieces of RAM is returned. The second branch becomes non-conductive and the second branch becomes conductive and appears as binary "1". Restoring to this opposite state is more inconvenient than direct and true recovery.

Accordingly, an object of the present invention is to manufacture an improved non-destructive stationary constant speed call memory piece and a memory device, and to have conductance or DC equilibrium, and to provide a stationary RAM in the connection relationship between the stationary RAM piece and the three non-destructive elements. A non-destructive stationary RAM device and a memory array are constructed in a device that gives capacity or dynamic imbalance to three pieces. In addition, an object of the present invention is to create a non-destructible stationary constant velocity calling memory fragment and a device in which the stationary RAM portion and the non-destructive portion of the memory fragments are appropriately separated, and the compact, high density, non-destructive stationary type with relatively simple manufacturing cost In manufacturing RAM fragments.

Another object of the present invention is to manufacture a non-destructive stationary RAM that does not cause DC current during programming at high voltage supply.

The present invention will be described in detail with reference to the accompanying drawings.

In general, the present invention is one of the two circuit memory state, and a variable point fixing device capable of writing and reading binary data to and from a decay bistable memory piece of semiconductor and a bistable decay semiconductor memory piece that accumulates binary data and BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-destructive semiconductor memory device composed of a non-destructive memory element capable of accumulating binary data as one of two potentials of a floating gate irrelevant to the memory state of the volatile memory fragment.

Furthermore, the device according to the present invention capacitively couples volatile memory pieces to the floating gate memory elements, replicates the memory state of stacked stable memory pieces to the floating gate elements, and capacitively couples the volatile semiconductor memory pieces to the floating gate elements. It is composed of a device that duplicates the memory state of a non-destructive floating gate, which is a non-destructive element, when power is applied to the memory fragments.

A device that duplicates the memory state of a bistable memory piece on a floating gate element and a device that duplicates the memory state of a floating gate element on a bistable memory piece both duplicate the memory state of the first circuit of a bistable piece on a floating gate element. Then, by copying the memory state of the floating gate element to the destructive pieces, the bistable pieces are operated to return to the original memory state. The bistable volatile memory fragments are flip-flop circuit elements that are interchangeably coupled as 4-6 transistors of stationary MOS, and the device according to the present invention is configured of a constant velocity memory array in a memory array according to a conventional method.

As will be generally described in the present invention, the particular examples illustrated in FIGS. 1 through 5 will be specifically described. Illustrated in FIGS. 1 to 5 is a non-destructive stationary constant velocity calling memory piece 10 according to the present invention.

The three pieces 10 are made up of a destructible stationary bistable flip-flop storage piece 12 and a floating gate element 14 capable of non-destructive current replacement. Since the three pieces 10 form part of the constant-speed call memory capable of specifying the X-Y address, these three pieces can also be used among other memory devices, but the destructive memory pieces 12 will be referred to as static RAM pieces later.

1 is a plan view showing a chip circuit. Device 10 represents a unit element of a polysilicon electrode structure. The circuit of the device 10 is shown in FIG. 5, and for the purposes of the present invention the circuit elements of the device 10 illustrated in FIG. 1 are illustrated in a somewhat simplified form in FIGS. have.

As illustrated in FIG. 1, the design of the three pieces 10 is relatively dense and the size of the unit pieces is about 82.5 microns x 79 microns and is a unit of the constant velocity calling arrangement.

In FIG. 2, the n-slice part of the silicon substrate 11 is formed in a straight line and crosses each other.

Moreover, in order to show the various polysilicon films of the superposition structure of the autonomous 10, it shows with the other line. In this regard, the shape of the primary polysilicon film 50 is a dot in a straight line. In addition, the secondary polysilicon film 52 has a x mark in a straight line, and the tertiary polysilicon film 54 is shown with the dotted line. The " embedded layers " 61 and 62 of the polysilicon film 54 connected to the n-channel portion are diagonal portions further narrowed in intervals.

In FIG. 1 and FIG. 2, the part connected by metal bonding is a diagonal connected rectangle.

In Fig. 5, the stationary RAM fragment 12 and the constant velocity call arrangement follow the conventional display method. The RAM segment 12 is written to three segments which sense or change the current state according to the conventional method by appropriately addressing and can be read from the segment. It is also possible to use a suitable RAM array connection and chip connection, such as storage line 100, V _{SS potential} line 102, V _{CC potential} line 104, Y data line 106 and complementary Y data line 108. I can record and read. These lines, shown above, are metal wires that transmit power and signals through an array (figure 2) connected to each of the three segments marked with a “x” in the path. The V _SS potential is about 0 volts, the V _CC potential is about 5 volts, and the substrate potential V _bb is about 3 volts. The non-destructive floating case element 14 and the stationary RAM fragment 12 are combined in a dynamic imbalance or a capacitive imbalance so that the current memory contents of the destructive stationary RAM fragment 12 are non-destructive element 14 according to an operator's intention. Store in In addition, the capacitive coupling device is configured so that the destructive stationary RAM fragment element 12 required by the operation of the appropriate circuit element can read the contents of the non-destructive floating gate element 14.

The contents of the stationary RAM fragment 12 and the non-destructive element 14 usually operate independently of one another except in the case of special copying requests. In particular, the current memory contents of the RAM segment 10 are not always stored in the non-volatile memory element 14 whenever the RAM segment 12 is written by the segment addressing and recording device, but rather according to a special "save" command. The operation of the capacitive replication circuit only stores the contents of the three pieces of the stationary RAM in the non-destructive element 14. Indeed, the non-volatile memory element 14 appears as a "potential ROM" programmable to the system 10.

As illustrated in FIG. 5, the device 10 is composed of a conventional 6-transistor stationary RAM piece 12 and a non-destructible floating gate memory element 14 capable of current replacement. The floating gate memory element 14 is of the type described in the patent application " substrate incorporating a floating gate memory fragment " which is also cited in the present invention.

An important non-destructive memory fragment element in the device according to the invention is an electrically insulating bias electrode located on the substrate surface adjacent to the floating gate and located within the substrate having opposite conductivity to the substrate. The bias electrode is located underneath the floating gate and the storage / storage electrode, which is located below the disappearance / storage electrode, which is isolated by the oxide. Since the bias electrode has a conductivity opposite to that of the substrate, it is electrically insulated from the substrate by the pn junction action under the influence of the reverse bias potential, and a device for insulating the bias electrode should be constructed in the apparatus. The basic function of the bias electrode is to capacitively bias the floating gate during capacitive injection (e.g. during write cycles) and during discharge from the floating gate (e.g. erase cycles).

The bias electrode potential is controlled by a switching circuit element or device. For example, when the transistor is operated, it is controlled by a transistor in the substrate of the device that connects the bias electrode to a predetermined reference voltage source.

When the switching device (ie, switching transistor) is turned off, the bias electrode is sufficiently '+' for the programming electrode under the floating gate, so that the electrons move by tunneling from the programming electrode toward the floating gate. The potential of the floating gate is changed. The potential shift of the floating gate to negative by electron transfer is sensed by a suitable sensing device such as a MOS transistor. Similarly, at least a portion of the vane / storage electrode overlaps and insulates the floating gate so that electron transfer occurs from the floating gate to the vane / storage electrode when the vane / storage electrode changes to a predetermined positive potential. By applying a relatively large (+) voltage to the floating gate in this way, it can be detected by a suitable device such as a sense transistor.

The feature of the self-regulating compensation circuitry of the memory is that it is physically formed in the area under the simultaneous floating gate, bias electrode and substrate, thus forming a current pulse into the floating gate during the write operation as electrons move from the program gate to the floating gate. Done. This circuit characteristic minimizes stress through tunnel oxide between the protrusions of the floating and programming gates.

However, after a considerable operating cycle, the charges in the oxides require a great deal of stress to write to the floating gate. These circuits are stressed as needed, so they automatically adjust to this condition. The initial stress on the floating gate and extra stress to compensate for the charged charge, which is a major factor in extending the required cycles of the device according to the present invention, must be given. Moreover, this feature is complemented by extremely dense aspects by constructing the semiconductor electrical characteristics of the bias electrode and the semiconductor surface of the substrate.

In this regard, in the electrically isolated state, the bias electrode functions as a variable capacitive coupling device that capacitively couples the large potential portion of the quenching / storing electrode with respect to the floating gate as a function of the floating gate potential. In this relationship, the capacitive coupling of the disappearance / storage electrode potential to the floating gate raises the potential sufficiently between the floating gate and the programming electrode, thereby moving electrons from the program electrode to the floating gate.

However, since the capacitance of the capacitive coupling device is variable, the disappearance / storage electrode potential portion coupled to the floating gate decreases as the potential of the floating gate decreases, and in particular, as the difference between the bias electrode potential and the floating gate potential increases. Will decrease. Therefore, the charge transfer from the programming electrode to the floating gate reduces the capacitive coupling, thus reducing the charge transfer to the floating gate.

As illustrated in the figure, the three-piece structure of the device is constructed on a single crystalline P-type silicon wafer substrate 11, in which the substrate 11 is about 1 × 10 ¹⁴ -1 × 10 ¹⁶ per cm ^3. Acceptable doping levels in the range of two atoms. An electrically insulated polysilicon floating gate 2 is constructed adjacent to the substrate, which is capacitively coupled to the bias electrode 7 in the substrate 11. A bias electrode 7 is formed in the substrate 10 taking the opposite conductivity form to the substrate 11 such that the level of donor impurities in the device 10 is about 1 × 10 ¹⁷ atoms / cm 3.

According to the conventional construction method, the bias electrode 7 is formed by diffusion or ion implantation, etc., and the thickness formed at this time is about 1 × 10 ¹² -1 × 10 ¹⁵ atoms / cm 2 by ion implantation of donor impurities. Make it about 1 micron.

The variable capacitance of the electrode relative to the extinction can be expressed as a function of the potential between the electrode and the substrate [Bayle and Smith (1070), "Charge Coupled Semiconductor Device", BellSystems Technical Journal, Vol. 49, pp 587 In the present invention, the variable capacitance cc2 of the floating gate 2 with respect to the bias electrode 7 can be expressed as follows.

In the above equation, Co is the maximum capacitance value per 1 cm 2 of the capacitor formed by the adjacent surface of the floating gate (2) given by the following equation.

In the above expression

ε: Dielectric constant of the SiO ₂ portion 5 between the floating gate 2 and the bias electrode 7.

Χ: thickness of the dielectric portion 5 between the floating gate 2 and the bias electrode 7.

q: electronic charge.

Ks is the relative dielectric constant of silicon.

Kd is the relative dielectric constant of the portion 5 separating the bias electrode 7 and the floating gate 2.

N: Doming density of the bias electrode 7.

: 바이어스 전극(7)의 전위(

N+)-부동게이트(2)의 전위(V_FG), 단, 이때 ΔV는 0보다 큰 값임.Δ

Is the potential of the bias electrode 7

The potential V _FG of the N +)-floating gate 2, provided that ΔV is greater than zero.

V _FB : Flat band voltage.

Therefore, CC2 becomes almost the same value as CO (constant) when the doping density (N) is extremely high, and changes to near zero when the doping density (N) is extremely low, with other variables being constant. Therefore, the capacitance CC2 is reduced as the floating gate 2 falls to the electron (-). However, when ΔV becomes less than or equal to 0, the capacitance CC2 is at a relatively constant maximum Co.

The variable capacitance CC2 controls the voltage connection of the floating gate 2 to the bias electrode 7, whereby the potential difference between the programming electrode and the moving gate through which the tunneling current flows is the doping density N of the bias electrode. By controlling it is effectively adjusted.

The illustrated constant speed recall memory piece 12 consists of two cross coupled stationary inverter circuits combined to form a stationary 6-transistor flip-flop memory device as a conventional MOS RAM type. In this relationship, the RAM memory 12 is connected to the cross-coupled flip-flon transistors 27 and 28 connected to the reduction pull-up transistors 31 and 32 through respective data junctions 29 and 30, respectively. It is composed.

cc)에 연결된다.The flip-flop transistors 27 and 28 are connected to the base terminal 24 while the reduction pull-up transistors 31 and 32 are connected to the RAM output terminal (

cc).

cc의 전위를 가하므로서 가증한데, 종래의 RAM조작 및 설계관례에 따라 기억배열 중의 "비트(bit)"선과 Y 및

에 번지지정된 세편(12)의 플립-플롭 절합점을 연결하고 X번지지정 트랜지스터를 작동시키도록 보충데이터 출력절합점(35,36)에 Y 번지지정선을 연결한다.Array ("row" or "word") "X" selection transistors 33 and 34 likewise have data junctions 29 and 30 for the purpose of selecting an array from among the entire storage arrays of which device 10 forms part. ) The selection of the three pieces 12 in each of the three arrays is made to the gate connecting one of the X addressing transistors 33 and 34 to one of the Y ["column"] addressing lines.

It is aggravated by applying the potential of cc. In accordance with the conventional RAM operation and design practice, the "bit" line and Y and

Connect the flip-flop junction point of the segment 12 to the addressed junction and connect the Y address line to the supplemental data output junction points 35 and 36 to operate the X address transistor.

cc)측에 "비트"선을 연결하여 둠으로 가능하게 된다. 플립-플롭의 상태에 따라〔트랜지스터(27)이나 (28)은 ON에 있게 되고 다른 것은 OFF가 될때〕전류는 "비트"선의 한곳 또는 다른 곳으로 흐르게 되며 읽기는 이 미분전류를 감지함으로서 가능해진다. 세편(12)에의 기록은 세편(12)을 번지지정하고 한개의 "비트"선을 전위(

cc)에 두고 다른 "비트"선을 기질의 전위(

ss)에 두므로서 종래의 방식으로 할 수 있게 된다.The reading of the three pieces 12 having a designated address is performed through a large value resistor,

It is possible to connect the "bit" line to the cc) side. Depending on the state of the flip-flop (when transistors 27 or 28 are on and others are off), current flows to one or the other of the "bit" lines and reading is possible by sensing this differential current. . Writing to three pieces 12 specifies that three pieces 12 are spread and one "bit" line

cc) and another "beat" line to the substrate potential (

ss), the conventional method is possible.

절합점(36)에 각각 나타나는 데이터 및 콜플리먼트 데이터와 함께 호출이 된다. 종래의 RAM읽기/ 쓰기 조작은 데이터 절합점(35,36)을 통해 실시되고 있는 것이다. 전력(

cc)이 계속적으로 세편(12)의 단자(26)에 공급되는 한 절합점(29,30)에서 나타나는 콤플리먼트 상태를 가진 트랜지스터(27,28,31,32)에 의해 교차 결합된 정지형 플립-플롭이 형성된다.Segment 12 is connected to Y junction point 35 through " word "" X " transistors 33 and 34.

The call is made with the data and collapsing data respectively appearing at the junction 36. The conventional RAM read / write operation is performed through the data junction points 35 and 36. power(

a stationary flip cross-coupled by transistors 27, 28, 31, and 32 with a complimentary state appearing at one junction point 29, 30 where cc is continuously supplied to the terminal 26 of the piece 12. -Flop is formed.

The stationary RAM pieces 12 can be made by known semiconductor processing methods and photolithography. Certain stationary RAMs are shown in the device 10 according to the present invention, where it can be appreciated that other suitable uses are possible. For example, in the device 10, transistors 31 and 32 are illustrated among the attenuation devices, but in other devices these transistors may be replaced with suitable resistors.

As described above, the RAM fragments are connected to the non-volatile memory device 14. The non-destructive fragment element 14 illustrated in the figure is composed of a floating gate 2, a device for transferring electrons to the floating gate 2, and a device for removing electrons from the floating gate. Furthermore, the fragment element 14 has an autonomous adjustment circuit to improve the number of write cycles in the non-destructive element 14. In practical operation, electrons transferred to the floating gate to impart a relatively negative potential storage state at the floating gate and electrons exiting the floating gate to impart a relatively positive potential storage state are non-destructive. A foundation for storing storage of the device 14 is formed.

Electronic tunneling is used to transfer or remove charges from the floating gate, which virtually eliminates any DC current from the high voltage programming source. The presence of a small amount of current for a high voltage source results in an on chip state at this voltage, which is an important advance in this field.

The sharp dolly in the non-obscurable device encourages tunneling currents, allowing the use of relatively thick oxides to separate the three tunneling elements and to deliver a significant amount of tunneling current entering and exiting the floating gate at a suitable voltage.

Another characteristic of the projection is that it mainly conducts tunnel current in a single direction and does not exhibit symmetric bidirectional current movement for the reverse electric field. This result is because the non-destructive element 14 is relatively unaffected by the memory state due to unnecessary early electron charge emission from the read operation or the operation of adjacent three pieces. The performance of non-destructive memory devices is controlled by the tunneling characteristics appearing between the polysilicon devices located above the substrate (which has static RAM fragments largely controlled by the shape of the substrate), so that the static RAM and non-non-volatile devices are independently controlled. Can be optimized. Therefore, many other methods can be easily used to synthesize static RAM fragments and non-volatile devices.

Capacitive coupling causes one of the junctions 29 in the RAM segment 12 to be capacitively coupled to the non-volatile memory 14 via a capacitance circuit element 23 and a transistor 8 having a capacitance of C ₁ . do. Complement data junction 30 is also capacitively coupled to non-destructive element 14 by coupling transistor 20 to capacitor circuit element 17 having a capacitance of C ₂ .

Various other circuit-binding elements will be described above, but it is important to note that the static RAM fragment 12 is only capacitively coupled to the non-destructive element 14. Since no DC compensation current flows through the flip-flop data junction point 29 or 30 due to the junction with the non-destructive element 14, the stationary RAM fragment 12 is in equilibrium in a normal state. This is an important improvement over the conventional method, and the operation time is also improved.

Figure 1 illustrates the electrode and floating gate structures of device 10, while Figure 2 illustrates the replacement of current in stationary RAM fragment 12 and device 10, along with a variety of transistors and capacitance elements of relatively suitable size. A topographic view of a non-destructive element 14 and a RAM segment 12 having a non-destructive element is shown.

3 and 4 are cross-sectional views of the device selected in FIG. 2, which is a so-called "source-drain doping" using only additional dielectric and metal deposition used for device assembly in accordance with conventional processing and alignment methods. doping) is a device assembly method called. The structure and operation of the non-destructive element 14 are several additional elements that form a connection to the stationary RAM fragment 12 in accordance with the contents of the currently pending patent (No. 344,354). The non-destructive fragment 14 utilizes three polysilicon films 50, 52, and 54 together with various substrate elements and isolation dielectrics during assembly, where the device 10 comprising the non-destructive fragment 14 is n. It is composed of channel MOS method, but other structures and designs are also available.

The non-destructive element structure (FIGS. 2-4) is constructed on a P-type silicon substrate 11, which includes a bias electrode 7 having a conductivity opposite to that of the substrate 11. The bias electrode is introduced by a conventional method such as a diffusion method or an ion implantation method. According to the conventional method, when grown to have a thickness of about 12000 kPa, a heat-insulating oxide 4 is formed on the substrate 11 to isolate the fragments. The thermal oxide then corrodes the floating gate, or non-destructive electrode portion, and reoxidizes the thin oxide films 5 and 6 to dielectrically insulate the next three deposit layers and the substrate, the next three deposit layers being conventional By photolithography, the polysilicon layer is corroded and oxidized to form connecting leads with programming electrodes 1, floating gates 2, evanescent / storage electrodes 3, and other circuit elements. The thermal oxides 5 and 6 which isolate the polysilicon film and the substrate are grown to a thickness of about 1000 kPa by a conventional method. The oxide thickness under the control gate of various transistors such as the coupling transistor 8 and the value of the substrate doping are appropriately selected so that the desired threshold voltage is obtained according to the conventional method and the gate of the transistor such as the transistor 8 is controlled. Is formed of a polysilicon film in the same manner as the three-piece structure.

The oxidation temperature of the primary polysilicon film is set to 1000 ° C., and the secondary polysilicon film is similarly applied to form projections 56 on the upper surface of the polysilicon film as shown by the saw blades shown in FIGS. 3 and 4.

The projections formed under these conditions have an area density of about 5x10 ⁹ / cm 2, which has an average bottom width of 456 mm 3 and an average height of 762 A.

If there is a projection, an extremely high electric field is formed even when a relatively low voltage is applied between overlapping and adjacent polysilicon films. When the projections are biased towards the negative side, the electric field is sufficiently capable of injecting electrons into relatively thick oxides (42,43) (they are 800-1000 kW), even at relatively low voltages (eg 25 volts or less). Is formed. Only one adjacent surface of the polysilicon film has protrusions, and when these protrusions are relatively biased to '+', tunneling of the electrons does not occur on the flat surface, thus exhibiting a diode-like effect. Projections vary in degree depending on conditions and are not limited to the specific examples above.

The various layers of polysilicon forming the floating gate and electrodes of the device 10 are insulated from each other with a SiO ₂ dielectric.

As illustrated in FIGS. 2 through 4, the overlapping portions 18 and 43 between the floating gate 2 and the programming electrode 1 are formed through an insulating oxide when a relatively sufficient positive voltage is present at the floating gate. The electron passes from the programming electrode to the floating gate. The overlap 25 between the extinction / storage gate 3 and the normal gate 2 passes electrons from the floating gate through the isolation oxide 42 when there is a relatively sufficient positive voltage at the gate 3. That's the part.

The gate 3 overlaps the portion 7 so that the voltage difference between the extinction / storage gate 3 and the bias electrode 7, the doping density N of the bias electrode, and the thickness and overlapping area of the insulating portion 6. To form a coupling capacitor 21 having a capacity of CC3 determined by. The floating gate 2 also overlaps the bias electrode 7 and is determined by the overlapping area and thickness of the insulating portion 5, the voltage difference of the moving gate 2 with respect to the bias electrode 7, and the doping density N. A coupling capacitor 22 having a capacitance CC2 is formed. The portion 9 is a heavily doped reference portion and is usually formed in the processing step of forming the source drain region of the processing transistor. The capacitance element 25 having the capacitance of CE, the capacitance element 19 having the capacitance of Csub, and the capacitance element 18 having the capacitance of C _P are configured as illustrated in the drawing, and the Indicate the various characteristics that come from structural elements. In this relationship, the division capacitor 23 having the total capacitance C1 is formed between the primary polysilicon film and the tertiary polysilicon film.

In addition to the capacitance of the gate of transistor 8 during the operating cycle (powering with potential V _CC ), this capacitor causes the junction point 29 to relax slightly more than the junction point 30 of the RAM segment 12. In this case, however, the transistor 20 is in a nonconductive state. A capacitor 17 having a capacitor C2 is formed between the primary polysilicon film and the substrate portion. As for the total capacitance of the capacitor C2 and the gate capacitance of the transistor 20, the total capacitance of the capacitor C1 and the gate capacitance of the transistor 8 rise slightly more slowly than the junction point 29 during the power increase. So that it is quite large. A capacitor 18 having a capacitor C _P is formed between the polysilicon floating gate of the transistor 20 and the primary polysilicon film 50.

This capacitor imparts a structure capable of electron movement from the programming electrode 1 of the primary polysilicon film 50 to the floating gate 2. If a sufficiently large electric field is generated in the capacitor 18 during programming, a tunnel occurs. A quench capacitor 25 having a capacitor CE is formed between the quenching / storage electrode 3 of the tertiary polysilicon film 54 and the floating gate 2.

This capacitor 25 imparts a structure for moving electrons from the floating gate 2 to the extinction / storage electrode 3. Tunneling occurs when a sufficiently large electric field is generated in the capacitor 25. Capacitor 25 also couples some potential to the floating gate during programming.

A capacitor 21 having a capacitor CC3 is formed between the extinction / storage electrode 3 and the bias electrode 7 having an n implantation type in the substrate. This capacitor provides potential coupling to the moving gate 2 through the capacitor 22 when the transistor 8 is turned off. A capacitor 22 having a capacitor CC2 is formed between the n-type implanted portion in the substrate of the floating gate 2 and the bias electrode 7. When the transistor 8 is in the non-conductive state, the potential is coupled from the extinction / storage electrode 3 (via the capacitor 21) to the bias electrode 7, and then again from the bias electrode 7 (capacitance). (22)] to the bias electrode (7) and then to the floating gate (2) through the bias electrode (7) through the bias electrode (7). If the transistor 8 is in the electric state and the voltage is applied to the electrode 3, the bias electrode 7 is at the ground potential and the capacitance 22 keeps the potential of the floating gate low so that a large electric field 25). The capacitor 19 having the capacitor Csub is an unnecessary parasitic p-n junction capacitor, which dissipates the capacitor 22 and the capacitor 21 from the dissipation / storage electrode 3 during programming. Therefore, this capacitor should be minimized.

The transistor 8 senses the state of the RAM fragments 12 and instructs the non-destructive element 14 to " program " or " disappear " in accordance with the storage state of the RAM fragments 12 and thereby It is a transistor that can be duplicated.

In addition, the transistor 20 is a transistor that connects the state of the non-destructive element 14 to the RAM segment 12. Careful attention is made to correlate these capacitances and the functions of the capacitors 21, 22, 17 and transistors 8, 20 in the operation of the pieces.

A three-layer polysilicon assembling method of n-channel silicon gates can be used to create a dense, easy-to-operate, non-destructive stationary RAM device 10 for use in microcomputers.

The arrangement of storage devices can also be used as conventional RAM with data storage capability at power down, i.e. as a destructive RAM with non-destructive ROM. The three pieces can store two separate data bits, one in the RAM portion 12 and one in each of the three non-destructive portions 14.

It is important to note that the RAM segment 12 is as independent of the ROM segment 14 and that non-volatile storage does not necessarily have to do so, as seen in all conventional RAM "write" cycles. Instead, non-destructive accumulation occurs because the "save" command is put on the memory array. In the RAM arrangement of the device 10, it is possible to use the RAM data pattern as a system capable of placing each corresponding non-destructive floating gate element. In this relationship, each corresponding non-destructive element portion of the array functions as a read-only memory (ROM) that can be replaced with a current.

The non-destructive element 14 will be referred to as ROM for the sake of simplicity. Because data is stored in the non-destructive ROM element 14 for the return to the RAM segment 12, this data accumulation function is useful in case of a total power loss or when the conventional RAM loses the data irretrievably. Can be used.

Moreover, since the RAM portion 12 and the ROM portion 14 are " transparent " mutually in the device 10, the RAM portion acts irrespective of the data state of the ROM portion. Because of this characteristic and the RAM part duplicates the true day state of the ROM part during power up, any starting program stored in the mask programmable ROM memory is automatically restored when the system power is restored. The RAM array portion of the storage array of the device 10 can be entered. The program or stored data in the ROM is preserved without time limitation and returned to the corresponding RAM fragment.

In operating the device 10 while continuing to supply the power at the potential V _cc to the RAM segment 12, the contents of the storage state of the stationary RAM portion 12 are copied to the ROM portion 14, wherein the on-chip or Depending on the off-chip, it is reproduced by applying a single "store" command pulse of about 25 volts to the decay / storage electrode 3 using an appropriate control circuit (not illustrated). . When power is removed from the RAM segment 12, the ROM 14 retains the data indefinitely or until used. When the operating power V _CC is applied to the stationary RAM 12 again, the data of the ROM portion 14 is automatically duplicated. Thus, the RAM 12 may be powered off, or more accurately, to store the data state in which the 25 volt "save" command pulse last appeared.

In operation, the junction point 29 of the bistable RAM fragment 12 is in a high state or a low state, and at this time, the junction point 30 has an opposite potential state. Attaching a capacitive coupling device that couples the RAM fragments 12 to the non-destructive element 14 so as to sense the storage state of the RAM fragments 12 while injecting electrons into the inequality gate 2 from the gate 2. The storage state of the RAM fragment 12 can be duplicated by determining whether to remove the former. In this relationship, when the junction point 29 is high, the transistor 8 becomes conductive, and the drain terminal of the transistor 8 grounds the large inversion plate (n-type) of the capacitors 21 and 22. If about 25 volts of " store " pulse is applied to the extinction / storage electrode 3, an electric field can be generated in the capacitor 25 to allow sufficient electrons to pass from the floating gate 2 to the electrode 3. This floating gate 2 becomes a gate of the transistor 20. If the entire circuit 10 is powered down (all voltages are lost) and then the RAM supply voltage (Vcc) is again powered up to about 5 volts, then the state of the non-destructive element 14 is transferred to the RAM segment 12. Is replicated.

In this case, the reduced load transistors 31 and 32 pull up the junction points 29 and 30, respectively. However, the transistor 20 is conductive and the capacitance of the junction point 30 and the capacitance C2 of the capacitor 17 and the gate capacitance of the transistor 20 are equal to the junction point (when its gate has + charge). Since the capacitance of the capacitor 29 and the capacitor C1 of the capacitor 23 and the gate capacitance of the transistor 8 become larger, the junction point 29 becomes close to one ball, so that the cross-coupled amplifier makes the intersection point 29 higher. When fixing and lowering the cutting point 30 is to be relaxed than the cutting point 29 in the device.

On the other hand, when the junction point 29 is low from the beginning, the transistor 8 is turned off (non-conductive), and the large n-type reverse plate in the capacitors 21 and 22 of the bias electrode 7 is floated. If a " store " pulse of about 25 volts is applied to the extinction / storage electrode 3, the capacitor 21 couples the potential to the floating gate 2 via the capacitor 22.

Likewise a 25 volt "store" voltage pulse is coupled to the floating gate 2 via a capacitor 25. The net effect is to have a sufficient electric field in the capacitor 18 to move electrons from the programming electrode 1 into the floating gate 2 to make the floating gate negative. When the floating gate becomes (-), the transistor 20 is turned off (non-conductive).

Thus, the entire circuit is powered down and the V _CC supply voltage is raised. Transistors 31 and 32 pull up junctions 29 and 30, respectively. However, in this case, the capacitance of the junction point 29 and the capacitance C1 of the capacitor 23 and the gate capacitance of the transistor 8 become larger than the capacitance of the junction point 30. (Transistor 20 is OFF).

Thus, the junction point 30 is somewhat larger than the junction point 29 so that the previous store pulse command causes the RAM state to replicate with respect to the floating gate element 14 so that the cross-coupled amplifier can also increase the junction point 30 significantly. The cutting point 29 is fixed small.

Therefore, in the operation of the device 10, the RAM fragments 12 may store a certain memory state (the cutting point 29 is made larger, the cutting point 30 is made smaller, or the cutting point 29 is made smaller, and the bonding point 30 is set. Enlarged state], the ROM portion 14 replicates the state in such a way that the RAM fragments 12 during power-up directly duplicate the same state of the ROM portion 14 again.

When the voltage supply V _CC is raised again for the data returned from the non-destructive ROM fragment 14 to the RAM fragment 12, various capacity relationships must be established. When the data is returned from the ROM segment 14 to the RAM segment 12 under the circuit condition in which the transistor 20 is turned off, the capacitor C1 of the capacitor 23 and the gate capacitance of the transistor 8 are sufficiently large so that the junction point is large. (29) always makes the pull-up much slower than the junction point 30, and the cross-linked amplifier of the RAM segment 12 can make the junction point 29 small (OFF) and the junction point 30 large (ON). Should be

For the return data from ROM fragment 14 to RAM fragment 12 when transistor 20 is ON, the capacitance C2 of capacitance 17 and the gate capacitance of transistor 20 are determined by capacitor 23. The cross-coupled amplifier of the RAM segment 12 must be large enough to fix the junction 30 smaller and the junction 29 larger than the capacitance C1 and the gate capacitance of the transistor 8.

Representative values for capacitance in these devices 10 are as follows.

Cutting point (29): about 0.10 picoparad

Cutting point 30 (transistor 20 in ON state): about 0.20 picoparad

Cutting point 30 (transistor 20 in OFF state): about 0.05 picoparad

As described in the pending patent application (No. 344, 354), the self-control circuit and the compensation circuit can be configured in a non-destructive device that can increase the number of cycles of use in the non-destructive device. Have.

As mentioned above, the array having a large number of these memories can be formed on a substrate chip by forming an appropriate support circuit and an interconnect device, thereby making a stationary RAM memory capable of non-destructive addressing. The data in the RAM subarray is duplicated for the corresponding ROM subarray and re-replicated to the RAM array upon power up of the RAM array.

Claims (1)

There are two different types of destructive semiconductor memory pieces 12 for storing binary data, devices 33, 34, 35, and 36 that are written to and read from the destructive memory pieces, and the floating gate conductor 2; A non-destructive memory consisting of an electrically insulated floating gate conductor 7 for storing binary data of one of the charge levels, and a capacitive coupling of the destructive memory fragments to a non-destructive memory device and the bi-stable to a floating gate conductor. Replicating the storage contents of the floating gate to the destructive memory element when power is applied to the device 8, 18, 21, 22, 25 and the destructive memory element for copying to the designated charge level according to the memory state of the memory element. A non-destructive stationary type or the like composed of devices 18 and 20 for capacitively coupling the floating gate of the non-destructive memory device to the destructive memory device for Call memory.

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