DE10211337B4 - Circuit arrangement and method of operating a circuit arrangement - Google Patents

Abstract

Circuit arrangement
• with an SRAM memory cell
With vertical transistors arranged such that the channel region extends orthogonal to the surface of a substrate in and / or on which the circuit arrangement is formed;
- With a first memory node to which a signal can be applied, and with a second memory node to which the inverse signal can be applied;
• with a buffer circuit
- With a first non-volatile memory cell, which is coupled to the first memory node;
- With a second non-volatile memory cell, which is coupled to the second memory node;
• which is set up so that in one
- first operating state
A first electrical potential on which one of the memory nodes is located is provided in such a way to the nonvolatile memory cell coupled thereto, thereby permanently bringing this nonvolatile memory cell into a first physical state,
A second electrical potential on which the other of the memory nodes ...

Description

The The invention relates to a circuit arrangement and a method for operating a circuit arrangement.

Three Basic types of semiconductor memories are static, dynamic and nonvolatile Storage.

A static semiconductor cell ("static random access memory ", SRAM cell) is a static semiconductor memory whose memory contents does not have to be constantly refreshed. Have SRAM memory the advantage of a high speed for programming or reading of information, however, is a registered information lost when the supply voltage is switched off. Two important ones Implementations of an SRAM memory cell are, on the one hand, an SRAM memory cell, having the six transistors, and on the other hand, an SRAM memory cell, the has four transistors and two ohmic resistors. An overview of SRAM memory cells is available for example [1].

A dynamic semiconductor cell ("dynamic random access memory ", DRAM cell) has as a memory cell a capacitor in which Charge state the information to be stored is coded. The addressing Such a memory cell is usually via a transistor switch, with a particular memory cell of an array of memory cells selected becomes. Due to recombination and leakage currents, the stored information goes However, a DRAM memory cell lost over time, so that the stored information must always be refreshed. Therefore has a dynamic semiconductor memory comparatively slow Programming and reading times on, and the energy needs to operate a dynamic semiconductor memory is high.

One example for a non-volatile one Semiconductor memory is an EEPROM ("electrically erasable and programmable read only memory "). An EEPROM allows the user often repeatable reading, Clear or programming. An important example of an EEPROM is the so-called floating gate memory. In a floating gate memory, the electric charge in the Floating gate, an electrically decoupled from the environment polysilicon structure, saved. The reloading is done by means of electrons, which are a thin gate-insulating Tunnel through layer between the semiconductor and the floating gate. A particularly space-saving non-volatile memory cell is the Flash EEPROM cell, in which by means of tunneling of hot electrons ("channel hot electron tunneling ") or using Fowler-Nordheim tunneling electrons in a gate-insulating Layer the layer. Bases of EEPROM technology are, for example described in [2]. EEPROM memory, however, have the disadvantage on that high electrical voltages especially for programming the information needed in the memory cells is what a lot waste heat and a high energy demand.

One another example of a known non-volatile Memory cell is the so-called PLED memory cell ("planar localized electron devices "), which is described, for example, in [3], [4], [5]. For a PLED memory is a floating gate for storing electrical charge carriers therefrom Environment through alternating layers of intrinsic silicon and a tunnel layer separated. By applying an electrical Voltage to a side gate At lateral areas, the arrangement of intrinsic silicon layers and tunneling layers are made electrically conductive, so that into the floating gate layer electric charge carriers can be injected. After switching off the side gate voltage, the charge is permanent stored in the floating gate layer. Such a programmed Information is readable by the electrical conductivity a channel region separated from the floating gate layer by an electrically conductive layer insulating layer is separated, is detected.

Indeed have non-volatiles Memory the disadvantage, compared to dynamic and static Semiconductor store a much longer write and read time to have, if the non-volatile Memory cells should have a sufficiently long hold time. In other words, it is difficult in a non-volatile Memory cell a long hold time with a short programming and To combine reading time.

Another type of semiconductor memory is the FRAM memory cell ("ferroelectric random access memory"). Basics about an FRAM memory cell are summarized in [6]. According to an example of a FRAM memory cell, a structure similar to that of the DRAM memory cell described above is used, except that a ferroelectric (eg, lead zirconate titanate, Pb (Zr _{1-x) is used} between the capacitor electrodes instead of a dielectric Ti _x ) O ₃ , PZT) is used. From the hysteresis curve of a ferroelectric, it can be concluded that the ferroelectric has a positive or a negative permanent polarization, depending on whether a positive or negative field strength (or voltage) is applied during programming. Reading is done by applying a positive voltage to the bit line. If a negative polarization is contained in the ferroelectric, there is a repolarization, so that a charge quantity flows to the bit line. With positive permanent polarization, the polarization changes only slightly, so that almost no charge flows to the bit line.

at the so-called MRAM ("magnetic random access memory ") the giant magnetoresistance effect (XMR effect) is exploited, wherein the operation of an MRAM memory cell, for example in [7]. An MRAM memory cell has a soft magnetic Electrode, a hard magnetic electrode and an interposed Tunnel layer on. By means of magnetizing the soft magnetic Electrode becomes information to be stored in the MRAM memory unit enrolled. This information can be obtained using the effect read out that the MRAM memory cell a much higher ohmic Resistance in mutually antiparallel orientation of the magnetization directions of the two ferromagnetic layers compared with the Case of a parallel orientation of the magnetization directions the two ferromagnetic layers.

Referring In the above description, an SRAM cell has the advantage of short programming and reading time, whereas they have the disadvantage has that when switching off the supply voltage in the SRAM memory cell stored information is lost. In contrast, points a non-volatile Memory the advantage, even in the absence of a supply voltage the Memory content for to store a sufficiently long hold time. However, that is Programming and reading time of a non-volatile memory cell often not short enough.

ST Microelectronics ^{TM is} pursuing the approach of operating an SRAM memory cell with a lithium battery in order to ensure a sustainable power supply for the SRAM memory. However, if the lithium battery fails or is empty, the memory contents of the SRAM cell may be lost.

Further An attempt is made to use a static memory cell with a non-volatile one To couple memory cell to shutdown or failure of a supply voltage those in the SRAM memory cell to buffer stored information on the nonvolatile memory cell, and when available again standing supply voltage to write back the information. In this connection, it is known from [8] an SRAM memory cell with a non-volatile Coupling SNOS ("silicon-nitride-oxide-semiconductor") memory, in which information by means of tunneling of charge carriers in a silicon nitride layer can be stored. At the [8] known architecture is an SRAM memory cell with four Transistors and two resistors used that opposite the Concept with six transistors are considered disadvantageous (see [1]). In particular, the scalability of a four-transistor SRAM cell for one CMOS process with structure dimensions of less than 100 nm as difficult viewed, allowing continued miniaturization is problematic. It is also with the method described in [8] difficult to find a memory cell with sufficiently fast programming and to get reading time. Also, the power loss in the from [8] known memory cell relatively large.

at a memory cell known from [9] is an SRAM memory cell with a FRAM memory cell coupled, for example, when switching off or in case of failure of a supply voltage in the SRAM memory cell to store stored information on the ferroelectric capacitances.

Especially the memory cells known from [8] and [9] have the disadvantage on that a desired miniaturization of the memory cells only very limited possible is. The minimum achievable structural dimension of the memory arrangement obtained is in particular due to the technological limitations in the available Masking techniques for forming the semiconductor memory limited. Especially the transistors of the memory device are not sufficiently small can be formed to a sufficiently high integration density of memory cells to obtain.

Of the The invention is based on the problem of providing a memory cell, which has sufficiently fast programming and reading times and safe from one Information loss due to switching off a supply voltage protected is, and with a sufficiently high density of integration of memory cells a memory cell array is reached.

The Problem is solved by a circuit arrangement and by a method for operating a circuit arrangement having the features according to the independent claims.

The inventive circuit arrangement has a SRAM memory cell with vertical transistors, with a first memory node, to which a signal can be applied, and with a second memory node, to which the inverse signal can be applied. Furthermore, the circuit arrangement comprises a latch circuit having a first nonvolatile memory cell which is connectable to the first memory node and a second nonvolatile memory cell which is connectable to the second memory node. The circuit arrangement according to the invention is set up in such a way in a first operating state, a first electrical potential, on which one of the memory nodes is located, being provided in such a way to the nonvolatile memory cell coupled therewith, thereby permanently bringing this nonvolatile memory cell into a first physical state, and a second electrical potential, on the other is the memory node, is provided to the so coupled other non-volatile memory cell, that this non-volatile memory cell is permanently brought into a second physical state. Furthermore, the circuit arrangement according to the invention is set up in such a way that in a second operating state, using the physical state of the first nonvolatile memory cell, the first memory node is brought to the electrical potential on which it was located in the first operating state and using of the physical state of the second nonvolatile memory cell, the second memory node is brought to the electrical potential on which it was in the first operating state.

clear In the SRAM memory cell, information to be stored is redundant or double, d. H. on the first memory node and (as to that inverse information) is stored on the second memory node. Should be in the SRAM memory cell For example, information with a logical value "1" stored For example, the first memory node becomes "high" electrical Potential is brought, and it will belong to the second memory node a "low" (i.e. lower than the high potential) potential. These in the stored electrical potentials of the two memory nodes Information can be cached in the cache circuit Be the electric charge on the first memory node to a node of the first nonvolatile memory cell and by the electric charge on the second memory node on a Node of the second nonvolatile memory cell is transferred. The charge states of the nodes of the two non-volatile ones Memory cells are therefore illustrative in the example described the "physical State "the non-volatile memory cells. Is the cached on the nodes of the non-volatile memory cells Charge on the first and second memory node of the SRAM memory cell transferred back, so be based on the physical states of nonvolatile Memory cells, the memory node to the previously occupied electrical potentials brought back, d. H. the stored information is stored in the SRAM memory cell written back.

According to the invention, a memory cell is provided which represents a combination of an SRAM memory cell with vertical transistors and nonvolatile memory cells. The transistors of the SRAM memory cell are vertical transistors, that is, transistors in which the conductive channel is orthogonal to the surface of a substrate in which the circuit arrangement is formed. A vertical transistor can be formed in a reduced dimension. Since the function-relevant parameters (eg, gate length) of a vertical transistor are set by means of a deposition instead of a structuring method, a significantly higher accuracy can be achieved when setting the parameters. For example, with the Atomic Layer Deposition (ALD) method, the vertical thickness of a layer can be adjusted down to a few Angstrom accuracy, whereas the smallest achievable horizontal structure dimension in a structuring process is on the order of 100 nm in current CMOS processes. This allows, in addition to increased reliability, continued miniaturization and shortened read and write times. Further, using vertical MOSFETs as transistors for an SRAM memory cell, according to the invention, it is possible to achieve a compact layout with an area requirement of 80.5 F ² for a memory cell. In this case, F stands for the smallest possible structure dimension in the context of a technology provided, that is, 1 F ² in a 100 nm technology would correspond to a base area of the memory arrangement of (100 nm) ² . Therefore, with a footprint equivalent to that of a conventional 6T SRAM cell, a memory element having an SRAM memory cell extended with the functionality of a nonvolatile memory cell is provided. Thereby, the advantages of a SRAM memory cell, in particular a fast access time, are combined with the advantages of a nonvolatile memory cell which maintains the stored information even in the event of a failure or shutdown of a supply voltage. Moreover, the circuit arrangement according to the invention can be used as a memory cell which can be operated in a low-power mode. In this low power mode, the information stored on memory nodes of the SRAM memory cell is cached on the nonvolatile memory cells, then the supply voltage can be turned off. At a later time, the supply voltage can be switched on again and the information cached on the nonvolatile memory cells can be written back into the SRAM memory cell. In other words, during the low power mode, the power consumption of the circuit arrangement is substantially reduced, thereby advantageously reducing the waste heat generated. In addition, the circuit arrangement according to the invention can be produced with little effort, since in the manufacturing process to mature, semiconductor standard techniques such as deposition, lithography and etching process can be used.

clear is according to the invention one of vertical MOSFETs formed SRAM memory cell with nonvolatile memory cells, such as EEPROM, MRAM or PLED memory cells using a favorable layout and with a skillful Wiring combined in such a way that a functionally integrated Component obtained in its compactness with a conventional planar Six-transistor SRAM cell comparable, but with a permanent memory function features. Possible Areas of application are fast cache memories, microprocessors or digital signal processors (DSP). The combined memory cell can also be used in a mobile electronic device (eg mobile phone, Laptop, "personal digital assistant "(PDA)) be used. Such a device can be turned off and when switching on again in the same place as before Power off working without a time-consuming boot process is required. In other words, the memory cell according to the invention be operated in a low power mode (power-down mode). In such a power-down mode, all power loss components are (eg leakage currents) of the SRAM cell array. Also allows local saving data non-volatile Memory a quick change of operating states power-down and active mode because the data is not covered by the full memory hierarchy in a non-volatile Memory of a hard drive must be routed. This will be energy saved as global capacity (for example, bus lines) or external capacities (off-chip capacity) not must be reloaded. The programming and activation process is preferably for all memory cells a memory cell array performed simultaneously because the data is stored locally in a respective non-volatile Memory cell to be cached, creating a serial Programming or reading cycle for backing up and writing back the data via the Data bus is avoided.

Of the Energy saving mode can also be used if certain Areas of a memory cell array in an operating state not active be used. The memory function is in this case of the nonvolatile Storage share met. Advantageously, can the SRAM transistors with very low threshold voltages and threshold voltages, which accelerates the access times in the active state. used one as non-volatile Memory element, a PLED memory cell, such as the tunnel barriers (eg, thickness and material) of the PLED memory cell in terms of access time and storage time to the requirements of the SRAM cell array flexible be adjusted. For example, a thin barrier for a quick change to energy-saving mode and for a low programming time be set. The according to the state the technology required control of non-volatile Memory cell with high electrical voltages (in some cases over 10 V) is avoided according to the invention for example, an optimized PLED cell with a voltage between 1.5 V to 3 V can be operated. This is special in terms of the fact that integrated circuit components are advantageous sensitive to a high electrical voltage and at a high electrical Tension to be destroyed can. This is a compatibility given with CMOS processes and logic circuits. Point of time To activate the power saving mode, for example, externally using a software-based control or by means of a hardware-implemented Procedure, and can each comply with the current performance requirements of the system or adapted to a user profile. Also is it is possible that the energy-saving mode is user-activated by the user.

If the circuit arrangement according to the invention is operated in a low-power, energy-saving mode the supply voltage of the SRAM cell array is switched off, after the stored information was previously stored locally in the non-volatile Memory cells for the Duration of power-down mode has been cached.

It should be emphasized that the integration density of the SRAM cell array is increased due to a compact layout, with an area requirement of 80.5 F ² (7 F × 11.5 F) achievable due to the use of vertical transistors. The functional extension results from the additional non-volatile memory part. This new functionally integrated device has the advantages of a six-transistor SRAM cell (low programming and reading voltages, fast access times) with advantages of nonvolatile memory cells such as EPROM, PLED, MRAM, FRAM, etc. (long hold time even without Supply voltage) can be combined.

Furthermore, a method for operating the circuit arrangement according to the invention with the features described above is provided according to the invention. According to the method, information is programmed, read or erased into the SRAM memory cell, or information programmed into the SRAM memory cell is latched in the latch circuit, or the SRAM memory cell is turned off, or it is latched in the latch circuit cached Informa programmed back into the SRAM memory cell.

preferred Development of the circuit arrangement of the invention will become apparent from the dependent ones Claims.

Preferably has at least one of the nonvolatile memory cells at least a vertical transistor.

According to one Such architectures are preferably all transistors of the circuit arrangement as vertical transistors designed so that the advantages described above, resulting from it that result for the SRAM memory cell Vertical transistors are used, even for the nonvolatile Memory cells apply.

Preferably The SRAM memory cell has six transistors.

Though the invention is not limited to a six transistor SRAM memory cell limited and is also for example a SRAM memory cell with four Transistors and two resistors applicable, however, it is particularly advantageous, the SRAM memory cell train with six transistors, as in such a scenario a very cheap Layout of the circuit arrangement results.

The Vertical transistors of the memory cells may be on a rectangular, be designed in particular square base.

At least some of the transistors may be field effect transistors and / or Be bipolar transistors.

Preferably the first electrical potential is the electrical potential of a Supply voltage (i.e., an upper reference potential) and the second electrical potential is the ground potential (i.e., a lower one) Reference potential).

At least one of the non-volatile Memory cells of the circuit arrangement according to the invention is preferably a PLED memory cell, an EEPROM memory cell, an MRAM memory cell or an FRAM memory cell.

It is an advantage of the invention that the inventive concept applicable to very different non-volatile memory cells and expandable, allowing the enumeration of nonvolatile memory cells Here is only an example and not exhaustive. In the description of the figure become practical implementations of the inventive concept exemplary for some of the mentioned types of nonvolatile memory cells are described.

in the Further embodiments of the method according to the invention for operating the circuit arrangement according to the invention. Embodiments of the circuit arrangement also apply to the method for operating the circuit arrangement according to the invention.

According to the procedure can in the SRAM memory cell programmed information in the Caching circuit to be cached by a first electrical potential on one of the memory nodes is located, so the coupled non-volatile Memory cell is provided that this non-volatile memory cell permanently brought into a first physical state, or by placing a second electrical potential on the other the memory node is located, so the coupled therewith other non-volatiles Memory cell is provided that this non-volatile memory cell permanently brought into a second physical state becomes.

The information stored in the latch circuit programmed back into the SRAM memory by using the physical state of the first nonvolatile Memory cell of the first memory node is brought to the electric potential on which the first memory node before caching the ones programmed in the SRAM memory Information was located in the cache circuit. Further, using the physical state of the second nonvolatile Memory cell of the second memory node to the electrical potential placed on the second memory node before caching programmed in the SRAM memory Information was located in the latch circuit.

embodiments The invention is illustrated in the figures and will be discussed below explained in more detail.

It demonstrate:

1 a circuit arrangement according to a first embodiment of the invention,

2A a circuit diagram of a circuit arrangement according to the first embodiment of the invention,

2 B a perspective schematic view of a realization of in 2A shown circuit arrangement according to the first embodiment of the invention,

2C a schematic layout plan view of in 2 B shown perspective view of the circuit arrangement according to the first embodiment of the invention,

3A a circuit diagram of a circuit arrangement according to a second embodiment of the invention,

3B to 3F schematic perspective views of layer sequences at different times during a method for producing a circuit arrangement,

3G a perspective schematic view of a realization of in 3A shown circuit arrangement according to the second embodiment of the invention, prepared according to the in 3B to 3F shown manufacturing method,

3H a schematic layout plan view of in 3G shown perspective view of the circuit arrangement according to the second embodiment of the invention,

4 a circuit diagram of a circuit arrangement according to a third embodiment of the invention.

In the following, reference is made to 1 a circuit arrangement 100 according to a first preferred embodiment of the invention.

The circuit arrangement 100 has an SRAM memory cell 101 on with vertical transistors, with a first memory node 102 (in 1 labeled "Q") to which a signal can be applied and to a second memory node 103 (the in 1 is denoted by "Q"), to which the inverse signal can be applied. For example, referring to 2A described in detail, are the storage nodes 102 . 103 suitably coupled to the vertical transistors of the SRAM memory cell. Furthermore, the circuit arrangement 100 a latch circuit 104 on with a first non-volatile memory cell 105 that with the first memory node 102 coupled to a second non-volatile memory cell 106 that connected to the second memory node 103 is coupled. The circuit arrangement 100 is arranged such that in a first operating state, the electrical potential V _DD 107 a supply voltage on which one of the memory nodes 102 or 103 is located, so the nonvolatile memory cell coupled thereto 105 or 106 is provided that this non-volatile memory cell 105 or 106 thereby permanently brought into a first physical state of charge. Furthermore, the circuit arrangement 100 set up such that in the first operating state, the electrical ground potential V _SS 108 on which the other is the storage node 102 or 103 is located, such as the other non-volatile memory cell coupled thereto 105 or 106 is provided that this non-volatile memory cell 105 or 106 thereby permanently brought into a second physical state of charge. Furthermore, the circuit arrangement 100 arranged such that in a second operating state using the physical state of charge of the first non-volatile memory cell 105 the first storage node 102 is brought to the electrical potential (V _DD or V _SS ) on which it was in the first operating state, and that in the second operating state using the physical state of charge of the second non-volatile memory cell 106 the second memory node 103 is brought to the electrical potential (V _DD or V _SS ) on which it was in the first operating state.

In other words, one on the first memory node 102 stored information, which as complementary information on the second memory node 103 is stored redundantly from the SRAM memory cell 101 on the first and the second non-volatile memory cell 105 . 106 of the latch circuit 104 be buffered, for example, a supply voltage source of the SRAM memory cell 101 shut off without affecting the circuit arrangement 100 stored information is lost. This functionality is provided by the nonvolatile memory cell 105 respectively. 106 fulfilled, which has the property of maintaining a stored information even when a power supply is turned off.

In the following, reference is made to 2A to 2C a circuit arrangement 200 according to the first preferred embodiment of the invention described in detail. Those components of the circuit arrangement 200 in the 1 shown circuit arrangement 100 have a corresponding element, are provided with the same reference numerals.

The first and second nonvolatile memory cells 105 . 106 are each formed as a PLED memory cell. The second electrical potential is the ground potential V _SS 108 , The first electrical potential is the potential V _DD 107 the supply voltage source.

As in 2A shows the SRAM memory cell 101 six vertical transistors, namely designed as a p-MOS transistor first flip-flop transistor 201 a second p-MOS transistor Flip-flop transistor 202 , a third flip-flop transistor designed as an n-MOS transistor 203 , a fourth flip-flop transistor formed as an n-MOS transistor 204 , a first switching transistor formed as an n-MOS transistor 205 and a second switching transistor formed as an n-type MOS transistor 206 , The vertical transistors of the circuit arrangement 200 are fabricated according to a method known in the art for fabricating vertical transistors as described in [10].

The cache circuit 104 has a first non-volatile memory cell designed as a PLED memory cell 105 and a second non-volatile memory cell, also designed as a PLED memory cell 106 on. The first nonvolatile memory cell 105 includes a first PLED memory cell transistor 208 and a first PLED layer sequence 209 on, by means of a first side electrode 210 is controllable. Analogously, the configured as a PLED cell second non-volatile memory cell 106 a second PLED memory cell transistor 211 , a second PLED layer sequence 212 and a second side electrode 213 on, by means of the second PLED layer sequence 212 is controllable. Furthermore, the latch circuit 104 a first control transistor 214 and a second control transistor 215 on. Furthermore, the latch circuit has 104 a voltage source for providing a first control voltage 216 a voltage source for providing a second control voltage 217 and a voltage source for providing a third control voltage 218 , The SRAM memory cell 101 has a first bit line 219 and a second bit line 220 on as well as a word line 221 ,

The first bit line 219 is with the first source / drain connection 205a of the first switching transistor 205 coupled, whose gate terminal is connected to the word line 221 is coupled. Further, the second source / drain terminal is 205b of the first switching transistor 205 with the first storage node 102 further coupled to the first source / drain terminal 201 of the first flip-flop transistor 201 is coupled. To the second source / drain connection 201b of the first flip-flop transistor 201 is the electric potential V _DD 107 the supply voltage source applied. Further, the first memory node 102 to the gate terminal of the second flip-flop transistor 202 coupled, whose first source / drain terminal 202a with the second memory node 103 is coupled. Further, the second memory node 103 with the second source / drain terminal 206b of the second switching transistor 206 coupled, whose first source / drain terminal 206a with the second bit line 220 is coupled. The gate connection 230 of the second switching transistor 206 is with the word pipe 221 coupled. Further, the second source / drain terminal is 202b of the second flip-flop transistor 202 with the second source / drain terminal 201b of the first flip-flop transistor 201 coupled. The gate terminal of the first flip-flop transistor 201 is with the second storage node 103 coupled. Further, the first memory node 102 with the first source / drain connection 203a of the third flip-flop transistor 203 coupled. To the second source / drain connection 203b of the third flip-flop transistor 203 is the electrical ground potential V _SS 108 This is also applied to the second source / drain connection 204b the fourth flip-flop transistor 204 is created. The first source / drain connection 204a the fourth flip-flop transistor 204 is with the second storage node 103 coupled. The gate terminals of the first flip-flop transistor 201 and the third flip-flop transistor 203 are with a first auxiliary node 222 coupled, and the gate terminals of the second flip-flop transistor 202 and the fourth flip-flop transistor 204 are with a second auxiliary node 223 coupled.

About the first and second auxiliary nodes 222 . 223 is the SRAM memory cell 101 with the latch circuit 104 coupled.

The first auxiliary node 222 is with the first source / drain connection 215a of the second control transistor 215 coupled, and the second source / drain terminal 215b of the second control transistor 215 is with the first source / drain connection 211 of the second PLED memory cell transistor 211 coupled. The second source / drain connection 211b of the second PLED memory cell transistor 211 is with the second source / drain terminal 208b of the first PLED memory cell transistor 208 coupled. To the second source / drain connections 208b . 211b the first and second PLED memory cell transistor 208 . 211 is the electric potential V _{ACT of} the third control voltage 218 created. To the gate terminal of the second control transistor 215 and the first control transistor 214 is the electrical potential of the first control voltage 216 V _REW created. The gate terminal of the second PLED memory cell transistor 211 is with an end portion of the second PLED layer sequence 212 coupled to the side of the second side electrode 213 is applied, which is at the electrical potential of the second control voltage 217 V _PRO is located. The other end portion of the second PLED layer sequence 212 is with the first auxiliary node 222 coupled. Further, the electric potential of the second control voltage 217 V _PRO also to the first side electrode 210 the first nonvolatile memory cell 105 created, and the one end portion of the first PLED layer sequence 209 is with the second Auxiliary node 223 coupled. The other end portion of the first PLED layer sequence 209 is connected to the gate region of the first PLED memory cell transistor 208 coupled, whose first source / drain terminal 208a with the second source / drain connection 214b of the first control transistor 214 is coupled. The first source / drain connection 214a of the first control transistor 214 is with the second electrical auxiliary node 223 coupled.

Below is the functionality of the circuit arrangement 200 described as a "non-volatile SRAM memory cell". This is done on the basis of the description of the method according to the invention for operating the circuit arrangement 200 ,

According to the method, either in the SRAM memory cell 101 Information is programmed, read or erased, or it gets into the SRAM memory cell 101 programmed information in the latch circuit 104 cached, or it becomes the SRAM memory cell 101 shut down, or it will be in the cache circuit 104 cached information in the SRAM memory cell 104 reprogrammed.

First, how will it be described in the SRAM memory cell 101 Information is programmed, read or deleted. According to the described embodiment, the electrical potential of the first control voltage for this operating mode 216 V _REW and the potential of the second control voltage 217 V _{PRO set} to the electrical ground potential. Then both are the first control transistor 214 as well as the second control transistor 215 as well as the first PLED memory cell transistor 208 as well as the second PLED memory cell transistor 211 non-conductive, leaving the SRAM memory cell 101 from the latch circuit 104 is electrically decoupled.

In this operating state, in the first memory node 102 or in the second memory node 103 Information will be inscribed. For this purpose, such an electrical voltage to the word line 221 created that the first switching transistor 205 and the second switching transistor 206 become conductive. Further, to the first bit line 219 and to the second bit line 220 such an electrical signal is applied to the first memory node 102 or the second memory node 103 is brought to a desired electrical potential. In the operation of a six-transistor SRAM memory cell, as in 2A shown frequently on the first store node 102 a given information is stored, and it is stored on the second memory node 103 a complementary information stored. Although it is not absolutely necessary for information to be stored to be stored directly and additionally as complementary, that is to say redundantly, in practice this is frequently carried out in such a way as to achieve a particularly high reliability of the stored information and to increase the error robustness of the SRAM. To ensure memory cell. For example, becomes the first storage node 102 brought to a "high" electrical potential, so this electrical potential is located at the gate terminals of the second flip-flop transistor 202 and the fourth flip-flop transistor 204 , As the second flip-flop transistor 202 a p-MOS transistor is, in this operating state, the second flip-flop transistor 202 non-conductive, whereas formed as n-MOS transistor fourth flip-flop transistor 204 is conductive. Simultaneously, the second electrical storage node 103 brought to a "low" electrical potential (ie lower than the "high" electrical potential "), so that the one with the second memory node 103 coupled gate terminal of the first flip-flop transistor 201 , which is formed as a p-MOS transistor, is electrically conductive, whereas that with the second memory node 103 coupled gate terminal of the third flip-flop transistor 203 , which is formed as n-MOS transistor blocks. Due to the described conductivity states of the first to fourth flip-flop transistors 201 to 204 is the first storage node 102 via the first flip-flop transistor 201 with the electrical potential V _DD 107 the supply voltage source coupled, whereas to the second memory node 103 via the conductive fourth flip-flop transistor 204 the electrical ground potential V _SS 108 is created. Is the electrical potential at the word line 221 shut off, leaving the first and second switching transistors 205 . 206 electrically non-conductive, so the impressed information is permanently in the first memory node 102 and as complementary information in the second memory node 103 saved.

To read this information is to the word line 221 applied such an electrical signal that thereby the first and the second switching transistor 205 . 206 become conductive. This will flow from the first storage node 102 in the first bit line 219 such an electric current, for the state of charge and for the stored information of the first memory node 102 is characteristic. Analog flows from the second memory node 103 via the second switching transistor 206 in the second bit line 220 such an electrical current for the in the second memory node 103 stored information is characteristic.

However, that goes in the first and second memory nodes 102 . 103 stored information is lost when the electrical supply voltage V _DD 107 is switched off. Before the information is lost, as will be described later, the circuit arrangement 200 protected.

Before switching off the supply voltage 107 can be in the SRAM memory cell 101 programmed information in the latch circuit 104 be cached.

This is done according to the invention by in the SRAM memory cell 101 programmed information in the latch circuit 104 is latched by a first electrical potential on which the first memory node 102 is located, so the nonvolatile memory cell coupled thereto 105 is provided that the first non-volatile memory cell 105 is permanently brought into a first state of charge. In addition, the SRAM memory cell 101 programmed information in the latch circuit 104 cached by a second electrical potential on which the second memory node 103 is located, so coupled to the second non-volatile memory cell 106 is provided that the second non-volatile memory cell 106 thereby permanently brought into a second state of charge.

In this backup phase, the SRAM memory cell 101 no longer described with information, that is, to the word line 221 no electrical signal is applied. In this operating state, the potential V _{REW is} the first control voltage 216 continue to a logical value "0", whereas the electrical potential V _{PRO of} the second control voltage 217 is brought to a logical value "1". This will be the first side gate electrode 210 and the second side gate electrode 213 brought to such an electrical potential that the first PLED layer sequence 209 and the second PLED layer sequence 212 a current flow in accordance with 2A allow horizontal direction, so that in the first memory node 102 stored information or charge through the first PLED layer sequence 209 to a first cache node 224 flows, the gate terminal of the first PLED memory cell transistor 208 is coupled. Analogously, the flows on the second memory node 103 stored information through the electrically conductive second PLED layer sequence 212 to a second cache node 225 connected to the gate terminal of the second PLED memory cell transistor 211 is coupled. Meanwhile, feedback is interrupted because the electrical potential V _{REW of} the first control voltage 216 is at a logical value "0". In this operating state, further, the electric potential V _{ACT of} the third control voltage 218 at a logical value "0".

If the previously on the first and second memory nodes 102 . 103 stored information / complementary information on the first and second buffer nodes, respectively 224 . 225 cached, the energy-saving mode can be initiated. For this purpose, the supply voltage source is turned off, and it becomes the signal of the second control voltage 217 brought to a logical value "0", whereby at the first and second side electrode 210 . 213 the electrical potential is adjusted so that the first PLED layer sequence 209 or the second PLED layer sequence 212 electrically non-conductive. This is a drain of the in the first and the second cache node 224 . 225 stored charge avoided. In this operating state is the SRAM memory cell 101 switched off, and the information permanently, that is vividly with a sufficiently high hold time, on the first and second cache nodes 224 . 225 the non-volatile memory cells 105 . 106 saved.

In this energy-saving mode, also called power-down mode, all electrical signals are deactivated. On the internal PLED memory cells 105 . 106 the data is stored permanently. The SRAM memory cell 101 does not consume any power loss since there are no potential differences at its nodes.

In a further method step according to the method for operating the circuit arrangement 200 that will be in the latch circuit 104 cached information in the SRAM memory 101 reprogrammed.

The reprogramming of the in the latch circuit 104 cached information in the SRAM memory 101 is done by using the state of charge of the first nonvolatile memory cell 105 the first storage node 102 is brought to the electric potential on which the first memory node 102 before caching in the SRAM memory cell 101 programmed information in the latch circuit 104 was and is done by using the state of charge of the second nonvolatile memory cell 106 the second memory node 103 is brought to the electric potential on which the second memory node 103 before caching in the SRAM memory cell 101 programmed information into the cache circuit 104 was located. Under the state of charge, the one on the first and second cache nodes 224 respectively. 225 gespeicher te electric charge understood.

Writing back the data from the nonvolatile PLED memory cells 105 . 106 begins with the reactivation of the supply voltage V _DD 107 the SRAM memory cell 104 , Since that on the first cache node 224 and those on the second cache node 225 stored information is complementary to each other, according to the stored information is either the first PLED memory cell transistor 208 or the second PLED memory cell transistor 211 electrically conductive. The activation of a write-back signal V _REW brings the first and the second control transistor 214 . 215 in a conductive state and establishes a coupling between the electrical potential of the third control voltage 218 and one of the two memory nodes 102 or 103 , depending on what information in the nonvolatile memory cells 105 . 106 is cached. By selecting a corresponding electrical potential V _ACT as a third control voltage 218 may be the voltage between the two source / drain terminals of each open transistor 208 or 211 be set so that the imbalance at the memory node 102 . 103 the SRAM memory cell 101 is sufficiently high and the write-back occurs with a boosted signal. Ideally, the setting of the SRAM flip-flop (formed from the four flip-flop transistors 201 to 204 ) on the rising edge of the reactivated supply voltage V _DD 107 , Since the programming voltage V _{PRO of} the second control voltage 217 is at a logical value "0", the memory contents of the nonvolatile memory cells remain 105 . 106 received, so that a lossless storage of the information is realized. When in the SRAM memory cell 101 stored information is not changed over several cycles of the process, in successive cycles only the negligible for the power loss balance portion of the lost charge components on the PLED buffer node 224 respectively. 225 added.

In the following, reference is made to 2 B a perspective view of a practical realization of in 2A shown circuit arrangement 200 described. Corresponding elements are in 2 B provided with the same reference numbers as in 2A , It should be noted that in 2 B for the purpose of a clear representation of electrically insulating areas, the mechanical stabilization and electrical decoupling of the electrically conductive components of the integrated circuit formed as a circuit arrangement 200 cause each other, are not shown.

Due to the superimposed representation of the individual components of the circuit arrangement 200 out 2 B is the exact structure and coupling of the transistors 201 to 206 . 208 . 211 . 214 . 215 not exactly apparent to each one of the transistors. In this regard, reference is made to the statements regarding the production of another embodiment of the circuit arrangement according to the invention, which is likewise designed as an integrated circuit, which production method is associated with FIG 3B to 3G is described.

In 2 B are a first and second coupling means 230 . 231 for electrically coupling the gate terminals of the first and second switching transistors 205 . 206 with the word line 221 shown. The first coupling agent 230 is made of polysilicon, whereas the second coupling means is made of a suitable metallic material. The components of the circuit arrangement 200 are on an electrically insulating silicon dioxide base layer 232 formed on a silicon substrate (not shown) is deposited. On the silica base layer 232 a further silicon layer (optionally also a silicide layer) is arranged, so that the silicon substrate, the silicon dioxide base layer 232 and the silicon disposed thereon form an SOI layer sequence ("silicon on insulator"). By structuring the upper silicon layer of the SOI layer sequence is a third coupling agent 233 formed, by means of which the second source / drain terminal 205b of the first switching transistor 205 , the first source / drain terminal 203a of the third flip-flop transistor 203 , the first source / drain terminal 201 of the first flip-flop transistor 201 , and the first source / drain terminal 214a of the first control transistor 214 are electrically coupled together. Further, by means of the third coupling means 233 the first source / drain connection 214a of the first control transistor 214 with a mesa structure 234 coupled. A mesa structure is a layer arrangement of a plurality of individual layers, in which island areas are structured by means of selective etching, so that integrated components are thereby formed. Referring to the circuit arrangement 200 are by means of the mesa structure 234 the first PLED layer sequence 209 and the second PLED layer sequence 212 educated.

It should be noted that the first PLED memory cell transistor 208 and the second PLED memory cell transistor 211 are not formed as vertical transistors according to the described embodiment. As in 2 B shown are the two source / drain connections 208a . 208b of the first PLED memory cell transistor 208 in surface areas of the mesa structure 234 educated. The gate connection of the first PLED memory cell transistor 208 is between the mesa structure 234 and the first PLED layer sequence 209 and between the source / drain terminals 208a . 208b arranged and in 2 B not shown separately. According to 2 B Therefore, the channel region of the first PLED memory cell transistor runs 208 horizontal. For the second PLED memory cell transistor 211 of which in 2 B only the second source / drain connection 211b While the other components are hidden, the same applies.

The first control transistor 214 is how in 2 B partially shown, formed as a kind of vertical transistor. As in 2 B shown are the two source / drain connections 214a . 214b formed in different layer planes and are also offset in the horizontal direction against each other. By means of the third coupling agent 233 is the first source / drain region 214a with one according to 2 B left sidewall of the mesa structure 234 coupled. A gate insulating layer is on the sidewall of the mesa structure 234 between the two source / drain terminals 214a . 214b intended. On the gate-insulating layer is laterally the gate terminal of the first control transistor 214 arranged (not shown) in coupling with a fifteenth coupling means 246 , by means of which to the gate terminal of the first control transistor 214 the potential V _REW can be applied. Similarly, the in 2 B mostly concealed second control transistor 215 educated.

The first source / drain connection 208a of the first PLED memory cell transistor 208 and the second source / drain terminal 214b of the first control transistor 214 are integrally formed.

Furthermore, by means of a fourth coupling means 235 the second source / drain region 206b of the second switching transistor 206 with the first source / drain connection 204a the fourth flip-flop transistor 204 , with the first source / drain connection 202a of the second flip-flop transistor 202 and with the first source / drain terminal 215a of the second control transistor 215 coupled. Furthermore, in 2 B a fifth coupling agent 236 shown by means of which the first source / drain terminal 205a of the first switching transistor 205 with the first bit line 219 is coupled. The first source / drain connection 206a of the second switching transistor 206 is by means of a sixth coupling agent 237 with the second bit line 220 coupled. By means of a seventh coupling agent 238 polysilicon are the gate terminal of the third flip-flop transistor 203 , the gate terminal of the first flip-flop transistor 201 and the second source / drain terminal 206b of the second switching transistor 206 coupled. By means of an eighth coupling agent 239 are the gate terminals of the second flip-flop transistor 202 and the fourth flip-flop transistor 204 together and with the second source / drain terminal 205b of the first switching transistor 205 coupled. Further, a ninth coupling agent 240 provided by means of which the second source / drain terminal 203b of the third flip-flop transistor 203 and the second source / drain terminal 204b the fourth flip-flop transistor 204 coupled to each other, and by means of the said terminals, the ground potential 108 can be applied. By means of a tenth coupling agent 241 are the second source / drain connections 201b . 202b the first and the second flip-flop transistor 201 . 202 coupled together, and by means of the tenth coupling means 241 is at the said connections the electrical potential V _{DD of} the supply voltage 107 applied. Further, an eleventh coupling agent 242 provided by means of which the first side electrode 210 and the second side electrode 213 are formed, wherein the eleventh coupling agent 242 of polysilicon material with a twelfth coupling agent 243 is coupled from a metallic material, by means of which twelfth coupling agent 243 the side gate electrodes 210 . 213 with the voltage source for providing the second control voltage 217 can be coupled.

Furthermore, the first PLED layer sequence 209 and the second PLED layer sequence 212 in 2 B shown. The first source / drain connection 214a of the first control transistor 214 is about a thirteenth coupling agent 244 with an end portion of the first PLED layer sequence 209 coupled. About a fourteenth coupling agent 245 , this in 2 B mostly from the first bit line 219 is concealed and has a similar structure as the thirteenth coupling agent 244 , is the first source / drain terminal 215a of the second control transistor 215 with an end portion of the second PLED layer sequence 212 coupled. By means of the fifteenth coupling agent 246 of polysilicon and by means of a sixteenth coupling agent 247 of a suitable metallic material are the gate terminals of the first control transistor 214 and the second control transistor 215 coupled to each other and is at both gate terminals that of the first control voltage 216 provided potential applied. Further, by means of a seventeenth coupling means 248 the second source / drain terminal 208b of the first PLED memory cell transistor 208 with the second source / drain terminal 211b of the second PLED memory cell transistor 211 coupled, and it is the electrical potential of the third control voltage 218 can be applied to the named connections. The mentioned coupling agents are in 2A provided with reference numerals.

In the following, reference is made to 2C a layout plan view of the circuit arrangement 200 according to the in 2C shown realization. The same components are provided with the same reference numbers.

As in 2C shown is the extent of the circuit arrangement 200 in accordance with 2C horizontal direction 7 F, whereas the extent of the circuit arrangement 200 in accordance with 2C vertical direction 11.5 F is. This results in an area requirement of the circuit arrangement 200 of 7 F × 11.5 F = 80.5 F ² .

In 2C the n-MOS vertical transistors are shown as bars and the p-MOS vertical transistors as double bars. First polysilicon elements 250 and second polysilicon elements 260 are in the legend of 2C Are defined. Furthermore, silicide areas are in the legend of 2C with reference number 270 Mistake. In addition, in the legend of 2C the representation of the mesa structures 234 Are defined. Metal contacts in one to the paper plane of 2C orthogonal direction are with crosses 280 . 281 . 282 characterized. It should be noted that in the layout view of 2C in particular, the fifteenth coupling means formed by means of a self-aligning process 246 only shown schematically.

In summary, the circuit arrangement 200 the benefits of a six-transistor SRAM cell 101 with the advantages of a permanent PLED memory 104 with optimization of the cell structure and layout, resulting in a circuit array having a rectangular footprint with an area requirement of 80.5 F ² on the surface of a substrate. It should be noted that the fabrication of the vertical MOSFETs may not necessarily be performed according to the method described in [10], but also according to a compatible alternative method. The choice of the fabrication method of the vertical transistors of the nonvolatile memory cells of the latch circuit depends on which type of nonvolatile memory is used for the latch circuit of the circuit arrangement according to the invention. The forming can optionally be done before, after or in time simultaneously with the vertical transistors of the SRAM memory cell.

In the following, reference is made to 3A a circuit arrangement 300 described according to a second embodiment of the invention. Such components, for those in the circuit arrangements 100 and 200 According to the above description, a corresponding element is provided, are provided with the same reference numerals.

In the circuit arrangement 300 are the non-volatile memory cells 105 . 106 designed as FRAM cells ("ferroelectric random access memory"). This is in the latch circuit 104 out 3A indicated that the first and second non-volatile memory cells 105 . 106 are shown with the circuit symbol of a variable capacitance. The functionality of an FRAM memory cell is described above and is essentially based on the fact that by applying a suitable electric field to a capacitor with a dielectric of a ferroelectric material, a permanent electric dipole moment of the ferroelectric dielectrics is generated and in this way the applied electric field is clear Is "saved".

The SRAM memory cell 101 the circuit arrangement 300 is the same as that of the circuit arrangement 200 , The coupling between the SRAM memory cell 101 and the latch circuit 104 again takes place by means of the first auxiliary node 222 or the second auxiliary node 223 , The first auxiliary node 222 is with the first source / drain connection 301 a first control transistor 301 coupled, whose second source / drain terminal 301b with the second cache node 225 is coupled. The second cache node 225 is connected to a terminal of the second non-volatile memory cell formed as a FRAM cell, that is, as a capacitor filled with a ferroelectric dielectric 106 coupled, at the other terminal, the electrical ground potential V _SS 108 is created. The second auxiliary node 223 is with the first source / drain connection 302a a second control transistor 302 coupled, whose second source / drain terminal 302b with the first cache node 224 is coupled. The first cache node 224 is connected to one terminal of the first nonvolatile memory cell configured as an FRAM memory cell 105 coupled, at the other terminal, the electrical ground potential V _SS 108 is created. A first control voltage V _RW 303 is connected to the gate terminals of the first and the second control transistor 302 coupled.

Below is the functionality of the circuit arrangement 300 as far as they are concerned by the functionality of the circuit arrangement 200 differs according to the first embodiment.

The programming, reading and erasing of information in the FRAM memory cell 101 takes place as described above.

To the low energy mode with the above the properties described in the first memory node 102 stored information or in the second memory node 103 stored complementary information in the first cache node 224 or in the second cache node 225 cached. It should be noted that the first and second nonvolatile memory cells formed as FRAM memory cells 105 . 106 are each formed as stacked capacitors ("stacked capacitor"), which is formed in or on the substrate. To the in the memory node 102 . 103 stored information in the FRAM memory cells 105 . 106 be temporarily store, before switching off the supply voltage V _DD 107 the SRAM memory cell 101 the two designed as n-MOS transistors control transistors 301 . 302 brought into a conductive state by the first control voltage 303 is set appropriately. This is a current flow, ie a transport of electrical charge carriers from the first storage node 102 through the second control transistor 302 on the first cache node 224 or to the according to 3A upper terminal of the designed as FRAM capacitor non-volatile memory cell 105 allows. Further, an equalization of the electrical charge between the second memory node 103 through the first control transistor 301 to the second cache node 225 or to the according to 3A upper terminal of the designed as FRAM capacitor non-volatile memory cell 106 allows. Clearly, the magnitude and sign of the permanent electric dipole moment of the ferroelectric dielectric of the FRAM capacitor 105 respectively. 106 a characteristic measure for those at the associated memory node 102 or 103 previously applied electrical charge carriers. Therefore, the information of the first or second memory node is 102 . 103 in the nonvolatile memory cells 105 respectively. 106 cached.

In the described operating state, the previously in the memory node 102 . 103 programmed information on the cache nodes 225 . 224 transferred and cached there, and it can after switching off the electrical potential V _{RW of} the first control voltage 303 also the electrical supply voltage V _DD 107 be switched off. In this state, no power dissipated and the information is in the latch circuit 104 permanently saved.

Before the write-back phase begins, the control transistors become 301 . 302 brought back into a conductive state by acting as the first control voltage 303 a corresponding electrical signal is set. Then the potential V _DD becomes the supply voltage 107 switched on. During the rising edge of the electrical potential V _DD 107 the supply voltage source cause the unequal FRAM capacitances (due to the different electrical dipole moments of the ferroelectric layers therein) a stronger or weaker coupling of the first node 102 or the second node 103 to the electrical ground potential V _SS 108 according to the different conductivity states of the third and the fourth flip-flop transistor 203 . 204 , This creates an asymmetry of the electrical charge at the first memory node 102 and at the second memory node 103 according to the information previously stored at this node. This becomes the six-transistor SRAM memory cell 101 switched back to the original state as soon as V _{DD has reached} the full voltage swing.

As from the simple structure of the circuit arrangement 300 As can be seen, in a design of the nonvolatile memory cells as FRAM memory cells, a less complex circuit architecture is achieved. It should be noted that the memory cell described also without the first control transistor 301 and the second control transistor 302 can be realized. In such a case, a circuit can be achieved with very little effort. An advantage of using control transistors 301 . 302 is that in the normal SRAM operation a secure electrical decoupling of the SRAM memory cell 101 from the latch circuit 104 is realized, resulting in reduced capacity at the first memory node 102 and the second memory node 103 result. Therefore, the write and read times are shorter in the normal SRAM operation, since only the gate / drain capacitances of the first and the second control transistor 301 . 302 are effective. In a circuit arrangement without control transistors 301 . 302 the full FRAM capacity would always be effective. It should also be noted that due to the stacked capacitor arrangement of the FRAM memory cells 105 . 106 an area-efficient implementation is ensured.

In the following, reference is made to 3B to 3G a method for producing a layer arrangement 300 described an implementation of the above with reference to 3A represents the circuit diagram described.

To the in 3B Layer sequence shown 310 To obtain an SOI substrate is first prepared. For this purpose, on a silicon substrate (not shown in FIG 3B ) a silicon dioxide layer is applied and on this silicon dioxide layer another silicon layer (or alternatively a silicide layer) is applied. This results in an SOI layer sequence ("silicon an insu Lator "), which is further structured using a lithography and an etching process. By means of structuring the SOI layer sequence, initially a rectangular, electrically insulating base area is formed 311 Of silicon dioxide material obtained in 3B is shown. The on the rectangular electrically insulating silicon dioxide base layer 311 arranged upper silicon layer is patterned such that thereby a first electrical coupling agent 314 and a second electrical coupling means 315 is trained. On or in the thus obtained first and second coupling agents 314 . 315 become the transistors 201 to 206 . 301 . 302 the circuit arrangement 300 designed as vertical transistors.

It should be noted that in 3B in addition to the layer sequence 310 a plurality of further vertical transistors (for example the further vertical transistor 312 ) associated with other circuit arrangements common to the circuit arrangement 300 be formed on or in the substrate, whereby a memory cell array is formed. The other vertical transistors are in 3B in order to illustrate the principle of arranging a plurality of circuit arrangements on a substrate, and for the purpose of a simplified illustration in FIG 3C to 3G not shown.

In the following, reference is made to 3B the structure of the other vertical transistor 312 described by way of example. Each of the vertical transistors of the circuit arrangement 300 can be configured as the other vertical transistor 312 out 3B , The vertical transistor 312 has a first source / drain connection 312a and a second source / drain terminal 312b , a first source / drain region 312c and a second source / drain region 312d , Between the first source / drain region 312c and the second source / drain region 312d is an undoped intermediate layer 312e arranged from a semiconductive material. In accordance with 3B vertical direction is the layer arrangement of the first source / drain region 312c , the intermediate layer 312e and the second source / drain region 312d sheathed with a thin gate insulating layer (not shown in FIG 3B ), and this gate insulating layer is covered by a gate electrode (not shown in FIG 3B ). By applying a suitable electrical voltage to the gate electrode is in the intermediate layer 312e creates a conductive channel, so that the layer arrangement 312 out 3B fulfills the functionality of a field effect transistor whose conducting channel in accordance with 3B vertical direction.

As in 3B are also shown the vertical transistors 201 to 206 . 301 . 302 on the rectangular electrically insulating base 311 educated. According to the circuit diagram 3A are the first source / drain connection 201 of the first flip-flop transistor 201 , the first source / drain terminal 203a of the third flip-flop transistor 203 , the first source / drain terminal 302a of the second control transistor 302 and the second source / drain terminal 205b of the first switching transistor 205 by means of the second coupling means 315 coupled from silicide material. Further, the first source / drain terminal 202a of the second flip-flop transistor 202 , the first source / drain terminal 204a the fourth flip-flop transistor 204 , the first source / drain terminal 301 of the first control transistor 301 and the second source / drain terminal 206b of the second switching transistor 206 by means of the first coupling means 314 coupled. Furthermore, in 3B further vertical transistors 312 of circuit arrangements shown in the circuit arrangement 300 are not affiliated.

To the in 3C Layer sequence shown 320 to receive, becomes a third coupling agent 321 Of polysilicon material deposited such that thereby the gate terminals of the first and the second switching transistor 205 . 206 be coupled. Furthermore, a fourth coupling agent 322 deposited, whereby the gate terminals of the first and second control transistor 301 . 302 be coupled with each other. In addition, a fifth coupling agent 323 deposited, whereby the gate terminals of the first and the third flip-flop transistor 201 . 203 and further providing said gate terminals to the first source / drain terminal 202a of the second flip-flop transistor 202 be coupled. In addition, a sixth coupling agent 324 , Also of polysilicon material deposited on the layer sequence such that thereby the gate terminals of the second and fourth flip-flop transistor 202 . 204 are coupled together, and further comprising said gate terminals to the first source / drain region 203a of the third flip-flop transistor 203 be coupled.

To the in 3D Layer sequence shown 330 to obtain a first and a second stack capacitor 331 . 332 educated. Each of these stack capacitors has two electrically conductive capacitor elements (illustratively the analog to capacitor plates in macroscopic capacitors) and a ferroelectric dielectric layer interposed therebetween (eg lead zirconate titanate, Pb (Zr _{1 -x} Ti _x ) O ₃ , PZT). In other words, the first and second stacking capacitors form 331 . 332 the two SRAM memory cells 105 . 106 , As in 3D shown, the first Sta pel capacitor 331 with the second source / drain terminal 302b of the second switching transistor 302 coupled, and it becomes the second stack capacitor 332 with the second source / drain terminal 301b of the first control transistor 301 coupled.

To the in 3E Layer sequence shown 340 to become a seventh coupling agent 341 on the first source / drain terminal 206a of the second switching transistor 206 deposited. Further, an eighth coupling agent 342 on a portion of the third coupling means 321 discontinued. In addition, a ninth coupling agent 343 on the first source / drain terminal 205a of the first switching transistor 205 discontinued. A tenth coupling agent 344 is on a portion of the fourth coupling agent 322 discontinued. An eleventh coupling agent 345 will be in the in 3E shown deposited and with the second source / drain connection 203b of the third flip-flop transistor 203 , with the second source / drain connection 204b the fourth flip-flop transistor 204 and with the according to 3E each upper electrically conductive capacitor elements of the first and second stacked capacitor 331 . 332 coupled. By means of the eleventh coupling agent 345 can be applied to the four components mentioned in each case the electrical ground potential V _SS (see. 3A ). Furthermore, a twelfth coupling agent 346 deposited on the layer sequence such that thereby an electrical coupling between the second source / drain terminal 202b of the second flip-flop transistor 202 and the second source / drain terminal 201b of the first flip-flop transistor 201 is realized.

To the in 3F Layer sequence shown 350 get the first bit line 219 designed such that it with the ninth coupling means 341 is coupled. Further, the second bit line becomes 220 formed such that this with the seventh coupling means 341 is electrically coupled. In addition, a thirteenth coupling agent 351 on the eighth coupling agent 342 trained, and it becomes a fourteenth coupling means 352 on the tenth coupling agent 344 educated.

To the in 3G shown circuit arrangement 300 get the word line 221 on the thirteenth coupling agent 351 trained, and it becomes a fifteenth coupling agent 360 on the fourteenth coupling agent 352 settled, by means of the fifteenth coupling agent 360 the electric potential V _RW to the gate terminals of the first and second control transistor 301 . 302 can be created.

In 3G is an integrated circuit arrangement 300 as realization of the circuit diagram 3A shown. The coupling elements off 3G one in 3A correspond to marked connection line are marked there with the corresponding reference numeral.

In 3H is a layout plan view of the circuit arrangement 300 shown which of the perspective view of 3G equivalent.

The transistors and wires are in 3H provided with the same reference numbers as in 3G , In particular, be on the legend of 3H referenced, as an outline 370 the surface area of the circuit arrangement 300 is apparent. Further, polysilicon elements 371 in the legend, by means of which in particular the couplings between gate terminals of the transistors involved in the in 3A . 3G shown manner are realized. Silicide elements 372 are further shown in the legend, by means of which in particular the source / drain terminals of the transistors involved are coupled together. Furthermore, first, second and third metal contacts 373 . 374 . 375 shown the corresponding electrical couplings in the direction perpendicular to the paper plane of 3H in the way shown there. Also are in 3H the word line 221 , the bit lines 219 . 220 as well as those lines 360 . 345 . 346 by means of which the electrical potentials V _RW , V _SS and V _DD to the corresponding terminals of the components of the circuit arrangement 300 be created.

Further, referring to FIG 4 a circuit arrangement 400 described according to a third embodiment of the invention.

The SRAM memory cell 101 the circuit arrangement 400 is designed in the same way as the SRAM memory cell 101 the circuit arrangement 200 , Therefore, structure and functionality of the SRAM memory cell 101 not described in detail below.

However, the cache circuit is 104 the circuit arrangement 400 Unlike in the previously described embodiments designed such that the latch circuit 104 the circuit arrangement 400 has two MRAM memory cells ("magnetic random access memory"). Illustratively, an MRAM memory cell is a variable ohmic resistor which, as described above, often consists of two ferromagnetic layers separated by a tunnel layer. The ohmic resistance of such a layer arrangement is higher when the two ferromagnetic layers have mutually antiparallel oriented magnetization directions than in the case parallel to each other oriented magnetization directions of both ferromagnetic layers.

The first auxiliary node 222 is with the designed as an MRAM memory cell second non-volatile memory cell 106 further coupled to the first source / drain terminal 401 a first control transistor 401 is coupled. The second source / drain connection 401b of the first control transistor 401 is with the first source / drain connection 402a a second control transistor 402 coupled. To the second source / drain connection 402b of the second control transistor 402 is the electrical ground potential V _SS 108 created. In contrast, the gate terminal of the second control transistor 402 coupled to the supply voltage V _DD . Further, the second source / drain terminal is 401b of the second control transistor 401 with the second source / drain terminal 403b a third control transistor 403 coupled, whose first source / drain terminal 403a with the first non-volatile memory cell, which is likewise designed as an MRAM memory cell 105 is coupled. The first nonvolatile memory cell 105 is also connected to the second auxiliary node 223 coupled. A first control voltage 404 is to the gate terminals of the first and the third control transistor 401 . 403 created. Furthermore, the latch circuit 104 a fourth control transistor 405 at whose gate terminal a second control voltage V _PRO1 406 is created. To the first source / drain connection 405a of the fourth control transistor 405 is the electrical potential V _DD 107 the supply voltage source applied. The second source / drain connection 405b of the fourth control transistor 405 is such with the variable resistors R ₁ and R _{2 of} the second and first non-volatile memory cell 106 respectively. 105 coupled, that at a given current flow through the fourth control transistor 405 the electrical resistance of the variable resistors R ₁ and R _{2 of} the second and first non-volatile memory cell 106 . 105 can be set to a predetermined value. Furthermore, the latch circuit 104 a fifth control transistor 407 on, at its first source / drain terminal 407a the potential V _DD 107 the electrical supply voltage source is applied, and its gate terminal to the first auxiliary electrical node 222 is coupled. The second source / drain connection 407b of the fifth control transistor 407 is with the second source / drain terminal 408b a sixth control transistor 408 and with the first source / drain terminal 409a a seventh control transistor 409 coupled. To the first source / drain connection 408a of the sixth control transistor 408 is the electrical ground potential V _SS 107 created. The gate terminal of the sixth control transistor 408 is with the first auxiliary node 222 coupled. To the gate terminal of the seventh control transistor 409 is a third control voltage V _PRO2 410 created. The second source / drain connection 409b of the seventh control transistor 409 is both with the second source / drain connection 411b an eighth control transistor 411 as well as with the second source / drain connection 412b a ninth control transistor 412 coupled.

It should be noted that the fifth control transistor 407 and the eighth control transistor 411 are formed as field-effect transistors of the p-type conductivity, whereas all other control transistors of the latch circuit 104 are formed as field effect transistors of the n-type conductivity.

The gate terminals of the eighth and ninth control transistors 411 . 412 are with the second auxiliary node 223 coupled, and to the first source / drain terminal 411a the eighth spike transistor 411 is the electrical potential V _DD 107 the supply voltage source applied. To the first source / drain connection 412a of the ninth control transistor 412 is the electrical ground potential V _SS 108 created.

Below is the functionality of the circuit arrangement 400 described.

In an operating state in which only the SRAM memory cell 101 to be operated (for example, for reading or programming information) are in particular the first and the third control transistor 401 . 403 non-conductive, which can be adjusted by appropriately adjusting the value of the first control voltage 404 is set.

If you want to switch to a low-power mode (power-down mode), you must switch to the first memory node 102 stored information or on the second memory node 103 stored thereto inverse information in the latch circuit 104 be cached. For this purpose, the two are first as non-volatile memory elements 105 . 106 used MRAM memory cells, that is, illustratively the variable resistors R ₁ , R ₂ , brought to a defined output state by by applying a suitable potential to the gate terminal of the fourth control transistor 405 this is brought into a conductive state. Then, a current I _{WR flows} , whereby the resistors R ₁ and R _{2 are brought} to a defined initial state. In other words, before the start of the power-down phase, the second control voltage V _{PRO1 is generated} by means of an electrical signal having a logical value "1" 406 a global write current for all circuit arrangements 400 (ie memory cell len) of a memory cell array. In this operating state, both the first control transistor 401 as well as the third control transistor 403 nonconductive, which by means of an electrical signal with the logic value "0" of the first control voltage 404 is realized.

Now, as in the first memory node 102 stored information or in the second memory node 103 stored information in the variable resistors R ₁ and R ₂ encoded in the value of the respective ohmic resistance buffered. For example, in a scenario, the first store node 102 at a logical value "1", whereas the second memory node 103 is at a logical value "0". Now consider the case that the seventh control transistor 409 conductive is what is met when using the third control voltage 410 V _PRO2 to the gate terminal of the seventh control transistor 410 an electrical signal with a logical value "1" is applied. In the considered scenario, the one with the first storage node 102 coupled eighth control transistor 411 , a p-MOS transistor, not conducting, since the first memory node 102 is at the logical value "1". In contrast, the ninth control transistor 412 , an n-MOS transistor, conducting, since its gate terminal to the first memory node 102 is coupled to the logical value "1". On the other hand, the second control node 103 at the logical value "0" with the gate terminals of the sixth control transistor 408 , an n-type MOS transistor, and the fifth control transistor 407 , a p-MOS transistor, coupled. Since the second memory node is at a potential having a logical value of "0", the fifth p-MOS control transistor is 407 conductive, whereas the sixth n-MOS control transistor 408 is non-conductive. Due to the described potential conditions, a current flows from the first source / drain terminal located at the potential V _DD 407a of the fifth control transistor 407 through the conductive fifth control transistor 407 , through the conductive seventh control transistor 409 and the leading ninth control transistor 412 , which at the electrical ground potential V _SS 108 is located, so on the local current loop 413 according to 4 an electric current flows counterclockwise due to the potential difference between V _DD and V _SS . It should be emphasized that the direction of electric current flow on the local current loop 413 depends on whether the first storage node 102 or the second storage node 103 is at the logical value "1". If the conditions are reversed than in the described scenario, the current loop occurs 413 a current flow according to 4 clockwise. The current flow on the local current loop 413 generates in dependence on the direction of rotation of a magnetic field whose orientation at the location of the first resistor R ₁ and at the location of the second resistor R _{2 is} antiparallel to each other. Thereby, the soft magnetic ferromagnetic layer of the two MRAM memory cells 105 and 106 oriented antiparallel to each other, so that in one of the MRAM memory cells 105 or 106 the resistor R ₁ or R _{2 takes} a higher value than in the other. Which resistor has the high and which resistor has the low electrical resistance depends on the orientation of the current flow on the local current loop 413 and therefore on the fact of whether the first memory node 102 or the second storage node 103 is at a logical value "1". In other words, the information is stored in the form of high or low resistance in R ₁ or R ₂ . The functionality is achieved by the described interconnection of the fourth control transistor 405 , the fifth control transistor 407 , the eighth control transistor 411 and the ninth control transistor 412 realized. Depending on the value of the logical signal on the first memory node 102 and on the second storage node 103 the current flows through the local current loop 413 left or right around. The current flow on the local current loop 413 is from the seventh control transistor 409 not interrupted, since in the described operating state as a third control voltage 410 V _PRO2 an electrical signal with a logic value "1" is set.

After completing this caching phase, the previously on the storage node 102 . 103 stored information and the complementary information stored on the resistors R ₁ and R ₂ , the vividly the latch nodes of the latch circuit 104 represent.

In the write-back phase, the different electrical resistance in R ₁ and R _{2 is} detected. This is done by means of the first control voltage 404 to the gate terminals of the first control transistor 401 and the third control transistor 403 an electric potential having a logical value "1" is applied, so that a predetermined electric current through the second control transistor 402 is divided on the two branches with the first variable resistor R ₁ and the second variable resistor R ₂ according to the values of these resistors. In other words, this current is distributed asymmetrically to the branches of the circuit arrangement 400 that with the first memory node 102 or with the second memory node 103 are coupled. This will point to the two memory nodes 102 . 103 the previously in the non-volatile memory cells 105 . 106 cached information is written back, whereby the conductivity of the first to fourth flip-flop transistors 201 to 204 is characteristically influenced in such a way that the cell in front of the Write-back ruling stable state tilts. In other words, there are the memory nodes 102 . 103 then back to the same state as before the caching, ie the information is written back. The tilting of the SRAM memory cell 104 in the associated stable state, if V _DD 107 has reached the full voltage swing.

• [1] Lage, C, Hayden, JD, Subramanian, C (1996) ”Advanced SRAM Technology – The Race Between 4T and 6T Cells”, IEDM 1996: 271–274
• [2] Widmann, D, Mader, H, Friedrich, H (1996) „Technologie hochintegrierter Schaltungen”, Kapitel 8.4.3, Springer Verlag, Berlin, IBSN 3-540-59357-8
• [3] Nakazato, K, Piotrowicz, PJA, Hasko, DG, Ahmed, H, Itoh, K (1997) ”PLED – Planar Localised Electron Devices” IEDM 1997: 179–182
• [4] Mizuta, H, Wagner, M, Nakazato, K (2001) ”The Role of Tunnel Barriers in Phase-State Low Electron-Number Drive Transistors (PLED-TRs)”, IEEE Transactions an Electron Devices 48(6): 1103–1108
• [5] Nakazato, K, Itoh, K, Ahmed, H, Mizuta, H, Kisu, T, Kato, M, Sakata, T (2000) ”Phase-state Low Electron-number Drive Random Access Memory (PLEDM)” IEEE International Solid State Circuits Conference 8/2000
• [6] Alexe, M, Harnagea, C, Hesse, D (2000) ”Nano-Engeneering für nichtflüchtige ferroelektrische Speicher”, Physikalische Blätter 56(10/2000): 47–50
• [7] Reiss, G et al. (1998) „Riesenmagnetowiderstand – Transfer in die Anwendung” Physikalische Blätter 4/98: 339–341
• [8] Herdt, CE (1992) ”Analysis, Measurement, and Simulation of Dynamic Write Inhibit in an nvSRAM Cell”, IEEE Transactions an Electron Devices, 39(5): 1191–1196
• [9] Miwa, T, Yamada, J, Koike, H, Toyoshima, H, Amanumqa, K, Kobayashi, S, Tatsumi, T, Maejima, Y, Hada, H, Kunio, T (2001) ”NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors” IEEE Journal of Solid-State Circuits, 36(3): 522–527
• [10] EP 0,920,060 A2

This document cites the following publications:

• [1] Lage, C, Hayden, JD, Subramanian, C (1996) "Advanced SRAM Technology - The Race Between 4T and 6T Cells", IEDM 1996: 271-274
• Widmann, D, Mader, H, Friedrich, H (1996) "Technology of highly integrated circuits", Chapter 8.4.3, Springer Verlag, Berlin, IBSN 3-540-59357-8
• [3] Nakazato, K, Piotrowicz, PJA, Hasko, DG, Ahmed, H, Itoh, K (1997) "PLED - Planar Localized Electron Devices" IEDM 1997: 179-182
• [4] Mizuta, H, Wagner, M, Nakazato, K (2001) "The Role of Tunneling Barriers in Phase-State Low Electron-Number Drive Transistors (PLED-TRs)", IEEE Transactions on Electron Devices 48 (6): 1103-1108
• [5] Nakazato, K, Itoh, K, Ahmed, H, Mizuta, H, Kisu, T, Kato, M, Sakata, T (2000) "Phase-State Low Electron-number Drive Random Access Memory (PLEDM)" IEEE International Solid State Circuits Conference 8/2000
• [6] Alexe, M, Harnagea, C, Hesse, D (2000) "Nano Engineering for Nonvolatile Ferroelectric Storage", Physical Sheets 56 (10/2000): 47-50
• [7] Reiss, G et al. (1998) "Giant Magnetoresistance - Transfer to Application" Physical Sheets 4/98: 339-341
• [8] Herdt, CE (1992) "Analysis, Measurement, and Simulation of Dynamic Write Inhibit on nvSRAM Cell," IEEE Transactions on Electron Devices, 39 (5): 1191-1196
• [9] Miwa, T, Yamada, J, Koike, H, Toyoshima, H, Amanumqa, K, Kobayashi, S, Tatsumi, T, Maejima, Y, Hada, H, Kunio, T (2001) "NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors "IEEE Journal of Solid-State Circuits, 36 (3): 522-527
• [10] EP 0,920,060 A2

Claims (10)

Circuit arrangement • with an SRAM memory cell With vertical transistors, which are arranged such that the channel region is orthogonal to the surface of a substrate, in and / or on which the circuit arrangement is formed is; - With a first memory node to which a signal can be applied, and with a second memory node, to which the inverse signal can be applied; • with a Latch circuit - with a first non-volatile Memory cell which is coupleable to the first memory node; - with a second non-volatile Memory cell which is connectable to the second memory node; • the like that is set up in one - first operating state - a first electrical potential on which one of the memory nodes is located is thus provided to the nonvolatile memory cell coupled thereto, that this non-volatile Memory cell thereby permanently in a first physical state is brought - one second electrical potential on which the other of the memory nodes is located, so coupled with the other non-volatile Memory cell is provided that this non-volatile memory cell permanently brought into a second physical state becomes,; - second operating condition - under Use of the physical state of the first non-volatile Memory cell of the first memory node to the electrical potential is brought, on which this is in the first operating state was; - under Use of the physical state of the second non-volatile Memory cell of the second memory node to the electrical potential is brought, on which this is in the first operating state was. Circuit arrangement according to claim 1, wherein at least one of the non-volatile Memory cell has at least one vertical transistor. Circuit arrangement according to claim 1 or 2, at the SRAM memory cell has six transistors. Circuit arrangement according to claim 2 or 3, at the vertical transistors of the memory cells on a rectangular Floor space are formed. Circuit arrangement according to one of claims 1 to 4, at least part of the transistors • field effect transistors or • bipolar transistors are. Circuit arrangement according to one of claims 1 to 5, in which the first electrical potential is a supply voltage and wherein the second electrical potential is the ground potential is. Circuit arrangement according to one of claims 1 to 6, wherein at least one of the nonvolatile memory cells • a PLED memory cell • an EEPROM memory cell An MRAM memory cell or an FRAM memory cell. Method for operating a circuit arrangement • with a Circuit arrangement - With an SRAM memory cell - With Vertical transistors, which are set up so that the Extends channel region orthogonal to the surface of a substrate, in and / or on which the circuit arrangement is formed; - with a first memory node to which a signal can be applied, and with a second memory node, to which the inverse signal can be applied is; - With a latch circuit - with a first non-volatile Memory cell which is coupleable to the first memory node; - with a second non-volatile Memory cell which is connectable to the second memory node; - the like that is set up in one - first operating state - a first electrical potential on which one of the memory nodes is located is thus provided to the nonvolatile memory cell coupled thereto, that this non-volatile Memory cell thereby permanently in a first physical state is brought - one second electrical potential on which the other of the memory nodes is located, so coupled with the other non-volatile Memory cell is provided, that this nonvolatile memory cell thereby permanently brought into a second physical state; - second operating condition • under Use of the physical state of the first non-volatile Memory cell of the first memory node to the electrical potential is brought, on which this is in the first operating state was; • under Use of the physical state of the second non-volatile Memory cell of the second memory node to the electrical potential is brought, on which this is in the first operating state was; • in which according to the method - either programmed into the SRAM memory cell information, read or deleted becomes; or - in the SRAM memory cell programmed information in the latch circuit is cached; or - The SRAM memory cell switched off becomes; or - in the buffer circuit information stored programmed back into the SRAM memory cell becomes. Method according to claim 8, in the SRAM memory cell programmed information is latched in the latch circuit is by • one first electrical potential on which one of the memory nodes is located, so the coupled non-volatile Memory cell is provided that this non-volatile memory cell permanently brought into a first physical state becomes; • one second electrical potential on which the other of the memory nodes is located, so coupled with the other non-volatile Memory cell is provided that this non-volatile memory cell permanently brought into a second physical state becomes. Method according to claim 9, in the latch circuit cached information back into the SRAM memory cell is by • under Use of the physical state of the first non-volatile Memory cell of the first memory node to the electrical potential is brought on top of the first memory node before caching the information programmed in the SRAM memory cell into the Caching circuit was located; • under use the physical state of the second nonvolatile memory cell, the second memory node is brought to the electric potential, on which the second Memory node before caching in the SRAM memory cell programmed information in the latch circuit located was.