DE10211337A1 - Circuit-arrangement with static random access memory cell, has non-volatile memory cells coupled respectively to first and second memory nodes - Google Patents

Abstract

A circuit-arrangement has a SRAM-memory cell, a temporary memory circuit, first and second non-volatile memory cells (105,106) coupled to first and second memory nodes (102,103) respectively such that, in a first operational state, a first electrical potential is available at one of the nodes and a second potential is available at the other node and, in a second operational state, the first memory node is placed at the electrical potential at which it was placed in the first operational state and the second memory node is placed at the electrical potential at which it was placed in the first operational state, by utilizing the physical state of the first and of the second non-volatile memory cells (105,106), respectively. An Independent claim is given for a method of running a circuit-arrangement

Description

The invention relates to a circuit arrangement and a Method for operating a circuit arrangement.

Three basic types of semiconductor memories are static, dynamic and non-volatile memory.

A static semiconductor cell ("static random access memory ", SRAM cell) is a static semiconductor memory, whose memory contents are not constantly refreshed got to. SRAM memory has the advantage of a high Speed for programming or reading information on, however, is a registered information lost when the supply voltage is switched off. Two important implementations of an SRAM memory cell are on the one hand, an SRAM memory cell, the six transistors and, on the other hand, an SRAM memory cell, the four Transistors and two ohmic resistors. A An overview of SRAM memory cells is given, for example [1].

A dynamic semiconductor cell ("dynamic random access memory ", DRAM cell) has a memory cell as one Capacitor on, in the state of charge to be stored Information is encoded. The addressing of such Memory cell is usually via a transistor switch, with which a particular memory cell of an array of Memory cells is selected. Due to recombination and leakage flows the stored information one However, DRAM memory cell lost over time, so that the stored information is always refreshed got to. Therefore, has a dynamic semiconductor memory comparatively slow programming and reading times, and the energy needed to operate a dynamic Semiconductor memory is high.

An example of a nonvolatile semiconductor memory is an EEPROM ("electrically erasable and programmable read only memory "). An EEPROM often allows the user repeatable reading, erasing or programming. On important example of an EEPROM is the so-called Floating gate memory. For a floating gate memory is the electrical charge in the floating gate, one of the Environment electrically decoupled polysilicon structure, saved. The reloading takes place by means of electrons, the one thin gate insulating layer between the semiconductor and tunnel through the floating gate. A particularly space-saving nonvolatile memory cell is the flash EEPROM cell, at the tunneling of hot electrons ("channel hot electron tunneling ") or using Fowler-Nordheim tunneling electrons tunnel into a gate-insulating layer. basis of EEPROM technology are described, for example, in [2]. EEPROM memory, however, have the disadvantage that high electrical voltages, in particular for programming the Information in the memory cells are required, which is a lot Waste heat and a high energy requirement.

Another example of a known non-volatile Memory cell is the so-called PLED memory cell ("planar localized electron devices "), which are described in [3], [4], [5] is described. For a PLED memory is a Floating gate for storing electrical charge carriers from its surroundings through alternating layers separated intrinsic silicon and a tunnel layer. By applying an electrical voltage to a side Gate can be on lateral areas of the arrangement intrinsic silicon layers and tunnel layers be made electrically conductive, so that in the floating Gate layer electric charge carriers are injected can. After switching off the side gate voltage is the Charge permanently stored in the floating gate layer. Such programmed information is readable by the electrical conductivity of a channel region of the floating gate layer by an electrically insulating Layer is separated, is detected.

Nonvolatile memories, however, have the disadvantage that compared to dynamic and static Semiconductor store a much longer write and To have read time if the nonvolatile memory cells should have a sufficiently long hold time. With In other words, it is difficult in a non-volatile Memory cell a long holding time with a short Programming and reading time to combine.

Another type of semiconductor memory is the FRAM memory cell ("ferroelectric random access memory"). Basics about an FRAM memory cell are summarized in [6]. According to an example of a FRAM memory cell, a structure similar to the DRAM memory cell described above is used, except that between the capacitor electrodes, instead of a dielectric, a ferroelectric (eg, lead zirconate titanate, Pb (Zr _1-x Ti _x ) O ₃ , PZT) is used. From the hysteresis curve of a ferroelectric, it can be concluded that the ferroelectric has a positive or a negative permanent polarization, depending on whether a positive or negative field strength (or voltage) is applied during programming. Reading is done by applying a positive voltage to the bit line. If a negative polarization is contained in the ferroelectric, a polarization occurs, so that an amount of charge flows to the bit line. With positive permanent polarization, the polarization changes only slightly, so that almost no charge flows to the bit line.

In the so-called MRAM ("magnetic random access memory") becomes the giant magnetoresistance effect (XMR effect) exploited, the operation of an MRAM memory cell For example, in [7] is described. An MRAM memory cell has a soft magnetic electrode, a hard magnetic Electrode and a tunnel layer arranged therebetween. By means of magnetizing the soft magnetic electrode an information to be stored in the MRAM memory unit enrolled. This information can be obtained using the Effect is read that the MRAM memory cell a much higher ohmic resistance to each other antiparallel orientation of the magnetization directions of has two ferromagnetic layers compared with in the case of a parallel orientation of the Magnetization directions of the two ferromagnetic Layers.

Referring to the above description, an SRAM cell the advantage of a short programming and reading time, whereas it has the disadvantage that when switching off the Supply voltage in the SRAM memory cell stored information is lost. In contrast, a non-volatile memory has the advantage, even in the absence a supply voltage the memory content for a to store sufficiently long hold time. However, that is Programming and reading time of a non-volatile memory cell often not sufficiently short.

The company ST Microelectronics ™ pursues the approach, a Operate SRAM memory cell with a lithium battery, for a permanent power supply to the SRAM memory guarantee. However, if the lithium battery fails or is empty, the memory contents of the SRAM cell get lost.

Furthermore, an attempt is made, a static memory cell with a nonvolatile memory cell to turn on at shutdown or in the event of a supply voltage failure, the voltage in the SRAM Memory cell stored information on the non-volatile memory cell, and at again available supply voltage the To write back information. In this context is off [8] known, an SRAM memory cell with a non-volatile SNOS memory ("silicon-nitride-oxide semiconductor "), in which an information means Tunneling of charge carriers in a silicon nitride layer can be stored. In the known from [8] Architecture becomes a SRAM memory cell with four Transistors and two resistors used opposite considered disadvantageous in the six transistor concept be (see [1]). In particular, the scalability a four-transistor SRAM cell for a CMOS process with Structural dimensions of less than 100 nm difficult so that continued miniaturization is problematic. Also it is with that described in [8] Method difficult to use a memory cell with a sufficient fast programming and reading time. Also is the power loss in the memory cell known from [8] relatively large.

In a memory cell known from [9], an SRAM Memory cell coupled to a FRAM memory cell to for example, when switching off or failure of one Supply voltage in the SRAM memory cell stored information on the ferroelectric To buffer capacities.

In particular, those known from [8] and [9] Memory cells have the disadvantage that a desired Miniaturization of memory cells only very limited is possible. The minimum achievable structural dimension of obtained memory arrangement is in particular by the technological limits in the available Masking techniques for forming the semiconductor memories limited. In particular, the transistors are the Memory arrangement not sufficiently small formable to a sufficiently high integration density of memory cells too receive.

The invention is based on the problem of a memory cell to create sufficiently fast programming and reading Times and safe from loss of information is protected as a result of switching off a supply voltage, and with a sufficiently high integration density of Memory cell of a memory cell array is reached.

The problem is due to a circuit arrangement and through a method of operating a circuit arrangement with the features solved according to the independent claims.

The circuit arrangement according to the invention has an SRAM Memory cell with vertical transistors, with a first Memory node to which a signal can be applied, and with a second memory node to which the inverse signal can be applied. Furthermore, the circuit arrangement has a Caching circuit on, with a first nonvolatile memory cell connected to the first memory Node is coupled and with a second non-volatile Memory cell which can be coupled to the second memory node is. The circuit arrangement according to the invention is such set up that in a first operating state, a first electrical potential on which one of the memory nodes is located, so the coupled non-volatile Memory cell is provided that these non-volatile Memory cell thereby permanently in a first physical state is brought, and that a second electrical potential on which the other of the storage Node is located, so the coupled with the other nonvolatile memory cell is provided that this nonvolatile memory cell permanently into a second physical state is brought. Furthermore, the Circuit arrangement according to the invention arranged in such a way that in a second operating state using the physical state of the first non-volatile Memory cell of the first memory node on the electrical Potential is brought on which this in the first Operating state, and that using the physical state of the second non-volatile Memory cell of the second memory node on the electrical Potential is brought on which this in the first Operating condition was located.

Illustratively, a memory to be stored is in the SRAM memory cell Information redundant or double, d. H. on the first Memory node and (as inverse information) on the stored second memory node. Should be stored in the SRAM Memory cell, for example, information with a logical value "1" are saved, for example the first storage node on a "high" electrical Potential brought, and it becomes the second memory node belonging to a "low" (i.e., lower than the high) Potential) potential. These in the electrical Potentials of the two memory nodes stored Information may be in the cache circuit be cached by the electric charge on the first memory node on a node of the first non-volatile memory cell and by the electrical Charge on the second memory node on a node of the second nonvolatile memory cell is transferred. The Charge states of the nodes of the two non-volatile Memory cells are therefore illustrative in the described Example of "physical state" of non-volatile Memory cells. Will the on the node of the non-volatile Memory cells cached charge on the first or second memory node of the SRAM memory cell be transferred back, so are based on the physical states of the nonvolatile memory cells the memory nodes on the previously occupied electrical Potentials returned, d. H. the stored information is written back to the SRAM memory cell.

According to the invention, a memory cell is provided which represents a combination of an SRAM memory cell with vertical transistors and nonvolatile memory cells. The transistors of the SRAM memory cell are vertical transistors, that is, transistors in which the conductive channel is substantially orthogonal to the surface of a substrate in which the circuit arrangement is formed. A vertical transistor can be formed in a reduced dimension. Since the function-relevant parameters (eg, gate length) of a vertical transistor are set by means of a deposition instead of a structuring method, a significantly higher accuracy can be achieved when setting the parameters. For example, with the Atomic Layer Deposition (ALD) method, the vertical thickness of a layer can be adjusted down to a few Angstrom accuracy, whereas the smallest achievable horizontal structure dimension in a structuring process is on the order of 100 nm in current CMOS processes. This allows, in addition to increased reliability, continued miniaturization and shortened read and write times. Further, using vertical MOSFETs as transistors for an SRAM memory cell, according to the invention, it is possible to achieve a compact layout with an area requirement of 80.5 F ² for a memory cell. In this case, F stands for the smallest possible structure dimension in the context of a technology provided, that is, 1 F ² in a 100 nm technology would correspond to a base area of the memory arrangement of (100 nm) ² . Therefore, with a footprint equivalent to that of a conventional 6T SRAM cell, there is provided a memory element with an SRAM memory cell which is extended by the functionality of a nonvolatile memory cell. Thereby, the advantages of a SRAM memory cell, in particular a fast access time, are combined with the advantages of a nonvolatile memory cell which maintains the stored information even in the event of a failure or shutdown of a supply voltage. Moreover, the circuit arrangement according to the invention can be used as a memory cell which can be operated in a low-power mode. In this low power mode, the information stored on memory nodes of the SRAM memory cell is cached on the nonvolatile memory cells, then the supply voltage can be turned off. At a later time, the supply voltage can be switched on again and the information cached on the nonvolatile memory cells can be written back into the SRAM memory cell. In other words, the power consumption of the circuit arrangement is substantially reduced during the low-power mode, which advantageously reduces the waste heat produced. In addition, the circuit arrangement according to the invention can be produced with little effort, since in the manufacturing process can be resorted to mature, semiconductor technology standard methods such as deposition, lithography and etching process.

Illustratively, according to the invention one of vertical MOSFETs formed SRAM memory cell with non-volatile Memory cells, for example EEPROM, MRAM or PLED Memory cells using a favorable layout and combined with a clever wiring such that a functionally integrated component is obtained which in its compactness with a conventional planar six- Transistor SRAM cell is comparable, however, over has a permanent storage function. Possible Application areas are fast cache memory, Microprocessors or digital signal processors (DSP). The combined memory cell can also be used in a mobile electronic device (for example, mobile phone, laptop, "personal digital assistant" (PDA)) are used. On such device can be turned off and a renewed Switch on at the same point as before switching off continue working without a time-consuming boot process is required. In other words, the Inventive memory cell in a low power mode (Power-down mode) are operated. In such a Power-down mode are all power loss components (eg leakage currents) of the SRAM cell array eliminated. Also, the local storage of data allows the non-volatile memory a quick change of the Operating states power-down and active mode as the data not through the full memory hierarchy into one non-volatile memory of a hard disk have to. This saves energy as global Capacities (for example of bus lines) or external Capacities (off-chip capacities) can not be reloaded have to. The programming and activation process will be preferably for all memory cells of a Memory cell array performed at the same time as the data locally in a respective nonvolatile memory cell cached, creating a serial Programming or reading cycle for saving and writing back data over the data bus is avoided.

The energy-saving mode can also be used if certain areas of a memory cell array in one Operating state can not be used actively. The Memory function is in this case of the non-volatile Storage share met. Advantageously, the SRAM Transistors with very low threshold voltages and Threshold voltages are running, what is the access times accelerated in the active state. Used as non-volatile memory element, a PLED memory cell, so For example, the tunnel barriers (eg, thickness and Material) of the PLED memory cell in terms of access time and storage time to the requirements of the SRAM cell array be flexibly adapted. For example, a thin Barrier for a quick change to energy-saving mode and set for a low programming time. The required according to the prior art control of non-volatile memory cell with high electrical Voltages (in some cases above 10 V) are according to the invention avoided, for example, because an optimized PLED cell with a voltage between 1.5 V to 3 V can be operated. This is particularly advantageous in view of the fact that integrated circuit components sensitive are at a high voltage and at too high a voltage can be destroyed. This is compatible with CMOS processes and Given logic circuits. The time to activate the Energy-saving mode, for example, externally using a Software-based control or by means of a Hardware implemented method, and can each to the current performance requirements of the system or to a Customized user profile. Also, it is possible that the energy-saving mode is user-defined by the user is activated.

When the circuit arrangement according to the invention in a energy-saving low-power mode, the Supply voltage of the SRAM cell array switched off after the stored information was previously stored locally in the non-volatile memory cells for the duration of the power Down mode has been cached.

It should be emphasized that the integration density of the SRAM cell array is increased due to a compact layout, with an area requirement of 80.5 F ² (7 F × 11.5 F) achievable due to the use of vertical transistors. The functional extension results from the additional non-volatile memory part. This new functionally integrated device offers the advantages of a six-transistor SRAM cell (low programming and reading voltages, fast access times) with advantages of nonvolatile memory cells such as EPROM, PLED, MRAM, FRAM, etc. (long hold time even without Supply voltage) can be combined.

Furthermore, according to the invention, a method for operating the circuit arrangement according to the invention with the above provided features described. According to the procedure are programmed into the SRAM memory cell information read or deleted, or it will be written to the SRAM Memory cell programmed information in the Caching circuit cached, or it the SRAM memory cell is turned off, or it is in the Caching circuit cached information programmed back into the SRAM memory cell.

Preferred development of the circuit arrangement of Invention will be apparent from the dependent claims.

Preferably, at least one of the non-volatile Memory cells at least one vertical transistor.

According to such an architecture, preferably all Transistors of the circuit arrangement as vertical Transistors are formed so that the ones described above Advantages resulting from the fact that for the SRAM Memory cell vertical transistors are used, too apply to the non-volatile memory cells.

Preferably, the SRAM memory cell has six transistors on.

Although the invention is not related to an SRAM memory cell is limited to six transistors and is also on, for example one SRAM memory cell with four transistors and two Resistors applicable, but it is special Advantageously, the SRAM memory cell with six transistors because in such a scenario a special favorable layout of the circuit arrangement results.

The vertical transistors of the memory cells can be on a rectangular, in particular square base be educated.

At least some of the transistors can be field-effect Transistors and / or bipolar transistors.

Preferably, the first electrical potential is the electrical potential of a supply voltage (i.e. upper reference potential) and the second electrical Potential the ground potential (i.e., a lower reference Potential).

At least one of the nonvolatile memory cells of The circuit arrangement according to the invention is preferably one PLED memory cell, an EEPROM memory cell, an MRAM Memory cell or an FRAM memory cell.

It is an advantage of the invention that the inventive Concept on very different non-volatile Memory cells is applicable and expandable, so the Enumeration of non-volatile memory cells here only exemplary and not exhaustive. In the Figure description will be practical implementations of inventive concept exemplifies some of mentioned types of nonvolatile memory cells described.

In addition, embodiments of the invention Method for operating the inventive circuit Arrangement described. Embodiments of the Circuit Arrangement also apply to the method of operating the inventive circuit arrangement.

According to the method, in the SRAM memory cell programmed information in the latch circuit be cached by a first electrical Potential that is located on one of the memory nodes is, so the coupled non-volatile Memory cell is provided that these non-volatile Memory cell permanently in a first physical State is brought, or by a second electrical Potential, which is located on the other of the memory nodes is so coupled with the other non-volatile Memory cell is provided that these non-volatile Memory cell thereby permanently in a second physical state is brought.

The stored in the latch circuit Information can be programmed back into the SRAM memory be by using the physical state the first nonvolatile memory cell of the first memory Node is brought to the electrical potential on the the first memory node before caching the in information programmed into the ERAM memory in the Caching circuit was located. Furthermore, can using the physical state of the second nonvolatile memory cell of the second memory node be brought to the electrical potential on which the second Memory node before caching in the SRAM Memory programmed information in the cache memory Circuit was located.

Embodiments of the invention are in the figures and will be explained in more detail below.

Show it:

Fig. 1 shows a circuit arrangement according to a first embodiment of the invention,

Fig. 2A is a circuit diagram of a circuit arrangement according to the first embodiment of the invention,

Fig. 2B is a perspective schematic view of an implementation of the shown in Fig. 2A circuit arrangement according to the first embodiment of the invention,

FIG. 2C is a schematic plan view of the layout in Fig. 2B perspective view of the circuit arrangement according to the first embodiment of the invention,

Fig. 3A is a circuit diagram of a circuit arrangement according to a second embodiment of the invention,

Fig. 3B to 3F are schematic perspective views of layer sequences at different times during a process for fabricating a circuit arrangement,

FIG. 3G is a perspective schematic view of an implementation of the circuit arrangement shown in FIG. 3A according to the second embodiment of the invention, made according to the manufacturing method shown in FIGS. 3B to 3F;

Fig. 3H is a schematic plan view of the layout in Fig. 3G perspective view of the Circuit arrangement shown, according to the second embodiment of the invention,

Fig. 4 is a circuit diagram of a circuit arrangement according to a third embodiment of the invention.

In the following, a circuit arrangement 100 according to a first preferred embodiment of the invention will be described with reference to FIG .

The circuit arrangement 100 comprises a vertical memory-type memory cell 101 having a first memory node 102 (labeled "Q" in FIG. 1) to which a signal can be applied and a second memory node 103 (which in Fig. 1 with " Q As will be described in detail with reference to Figure 2A, for example, the storage nodes 102 , 103 are suitably coupled to the vertical transistors of the SRAIVT memory cell 100 includes a latch circuit 104 having a first nonvolatile memory cell 105 coupled to the first memory node 102 and a second nonvolatile memory cell 106 coupled to the second memory node 103. The circuitry 100 is such that, in a first operating state, the electrical potential V _DD 107 of a supply voltage on which one of the memory nodes 102 or 103 is located is provided to the nonvolatile memory cell 105 or 106 coupled therewith, such nonvolatile memory cell 105 or 106 thereby permanently in a first physical state of charge t will. Further, the circuit arrangement 100 is configured such that, in the first operating state, the electrical ground potential V _SS 108 on which the other of the memory nodes 102 or 103 is located is provided to the other nonvolatile memory cell 105 or 106 coupled thereto This non-volatile memory cell 105 or 106 is thereby permanently brought into a second physical state of charge. Further, the circuit arrangement 100 is configured such that, in a second operating state, using the physical state of charge of the first nonvolatile memory cell 105, the first memory node 102 is brought to the electric potential (V _DD or V _SS ) on which it is stored was in the first operating state, and that in the second operating state using the physical state of charge of the second nonvolatile memory cell 106, the second memory node 103 is brought to the electrical potential (V _DD or V _SS ), in which it was in the first operating state ,

In other words, information stored on the first memory node 102 , which is redundantly stored as complementary information on the second memory node 103, may be stored from the SRAM memory cell 101 to the first and second non-volatile memory cells 105 , 106, respectively, of the cache Circuit 104 may be latched, for example, to turn off a supply voltage source of the SRAM memory cell 101 without losing the information stored in the circuit arrangement 100 . This functionality is fulfilled by the nonvolatile memory cell 105 or 106 , which has the property of maintaining stored information even when the supply voltage is switched off.

Furthermore 2A is a circuit arrangement, referring to FIG. To FIG. 2C described the first preferred embodiment of the invention in detail according to 200th Those components of the circuit arrangement 200 which have a corresponding element in the circuit arrangement 100 shown in FIG. 1 are provided with the same reference numerals.

The first and second nonvolatile memory cells 105 , 106 are each formed as a PLED memory cell. The second electrical potential is the ground potential V _SS 108 . The first electrical potential is the potential V _DD 107 of the supply voltage source.

As shown in FIG. 2A, the SRAM memory cell 101 has six vertical transistors, namely, a first flip-flop transistor 201 formed as a p-MOS transistor, a second flip-flop transistor formed as a p-MOS transistor 202 , a third flip-flop transistor 203 formed as an n-type MOS transistor, a fourth flip-flop transistor 204 formed as an n-type MOS transistor, a first switching transistor 205 formed as an n-type MOS transistor, and one as n-MOS transistor formed second switching transistor 206th The vertical transistors of the circuit arrangement 200 are fabricated in accordance with a method known in the art for fabricating vertical transistors, as described in [10].

The latching circuit 104 has a first nonvolatile memory cell 105 formed as a PLED memory cell and a second nonvolatile memory cell 106 also embodied as a PLED memory cell. The first nonvolatile memory cell 105 has a first PLED memory cell transistor 208 and a first PLED layer sequence 209 , which can be controlled by means of a first side electrode 210 . Analogously, the second non-volatile memory cell 106 embodied as a PLED cell has a second PLED memory cell transistor 211 , a second PLED layer sequence 212 and a second side electrode 213, by means of which the second PLED layer sequence 212 can be controlled. Furthermore, the latch circuit 104 has a first control transistor 214 and a second control transistor 215 . Further, the latch circuit 104 has a voltage source for providing a first control voltage 216 , a voltage source for providing a second control voltage 217, and a voltage source for providing a third control voltage 218 . The SRAM memory cell 101 has a first bit line 219 and a second bit line 220 and a word line 221 .

The first bit line 219 is coupled to the first source / drain terminal 205 a of the first switching transistor 205 , whose gate terminal is coupled to the word line 221 . Furthermore, the second source / drain terminal 205 b of the first switching transistor 205 is coupled to the first memory node 102 , which is further coupled to the first source / drain terminal 201 a of the first flip-flop transistor 201 , At the second source / drain terminal 201 b of the first flip-flop transistor 201 , the electrical potential V _DD 107 of the supply voltage source is applied. Furthermore, the first memory node 102 is coupled to the gate terminal of the second flip-flop transistor 202 , whose first source / drain terminal 202 a is coupled to the second memory node 103 . Furthermore, the second memory node 103 is coupled to the second source / drain terminal 206 b of the second switching transistor 206 , whose first source / drain terminal 206 a is coupled to the second bit line 220 . The gate terminal 230 of the second switching transistor 206 is coupled to the word line 221 . Furthermore, the second source / drain terminal 202 b of the second flip-flop transistor 202 is coupled to the second source / drain terminal 201 b of the first flip-flop transistor 201 . The gate terminal of the first flip-flop transistor 201 is coupled to the second memory node 103 . Furthermore, the first memory node 102 is coupled to the first source / drain terminal 203 a of the third flip-flop transistor 203 . To the second source / drain terminal 203 b of the third flip-flop transistor 203 , the electrical ground potential V _SS 108 is applied, which is also applied to the second source / drain terminal 204 b of the fourth flip-flop transistor 204 is. The first source / drain terminal 204 a of the fourth flip-flop transistor 204 is coupled to the second memory node 103 . The gate terminals of the first flip-flop transistor 201 and the third flip-flop transistor 203 are coupled to a first auxiliary node 222 , and the gate terminals of the second flip-flop transistor 202 and the fourth flip-flop -Transistors 204 are coupled to a second auxiliary node 223 .

Through the first and second auxiliary nodes 222 , 223 , the SRAM memory cell 101 is coupled to the latch circuit 104 .

The first auxiliary node 222 is coupled to the first source / drain terminal 215 a of the second control transistor 215, and the second source / drain terminal 215 b of the second control transistor 215 is connected to the first source / Drain terminal 211 a of the second PLED memory cell transistor 211 is coupled. The second source / drain terminal 211 b of the second PLED memory cell transistor 211 is coupled to the second source / drain terminal 208 b of the first PLED memory cell transistor 208 . To the second source / drain terminals 208 b, 211 b of the first and second PLED memory cell transistor 208 , 211 , the electrical potential V _{ACT of} the third control voltage 218 is applied. To the gate terminal of the second control transistor 215 and the first control transistor 214 , the electric potential of the first control voltage 216 V _{REW is} applied. The gate terminal of the second PLED memory cell transistor 211 is coupled to an end portion of the second PLED layer sequence 212 , to which the second side electrode 213 , which is at the electrical potential of the second control voltage 217 V _PRO, is laterally applied is. The other end portion of the second PLED layer sequence 212 is coupled to the first auxiliary node 222 . Further, the electric potential of the second control voltage 217 V _{PRO is} also applied to the first side electrode 210 of the first nonvolatile memory cell 105 , and the one end portion of the first PLED layer sequence 209 is coupled to the second auxiliary node 223 . The other end section of the first PLED layer sequence 209 is coupled to the gate area of the first PLED memory cell transistor 208 , whose first source / drain terminal 208 a is connected to the second source / drain terminal 214 b of the first control circuit. Transistor 214 is coupled. The first source / drain terminal 214 a of the first control transistor 214 is coupled to the second auxiliary electrical node 223 .

In the following, the functionality of the circuit arrangement 200 will be described as a "nonvolatile SRAM memory cell". This is done on the basis of the description of the method according to the invention for operating the circuit arrangement 200 .

According to the process is either programmed into the SRAM memory cell 101 information, read or deleted, or is latched in the SRAM memory cell 101 programmed information in the latch circuit 104, or it is turned off, the SRAM memory cell 101, or it will cached information into the latch circuit 104 is programmed back into the SRAM memory cell 104 .

First, how to program, read or erase information into the SRAM memory cell 101 will be described. According to the described embodiment, the electrical potential of the first control voltage 216 V _REW and the potential of the second control voltage 217 V _{PRO is set} to the electrical ground potential for this operating mode. Then, both the first control transistor 214 and the second control transistor 215 as well as the first PLED memory cell transistor 208 and the second PLED memory cell transistor 211 are non-conductive, so that the SRAM memory cell 101 from the latch Circuit 104 is electrically decoupled.

In this operating state, information can be written into the first memory node 102 or into the second memory node 103 . For this purpose, such an electrical voltage is applied to the word line 221 that the first switching transistor 205 and the second switching transistor 206 become conductive. Further, to the first bit line 219 and the second bit line 220 , such an electrical signal is applied that the first memory node 102 and the second memory node 103 are brought to a desired electrical potential. In the operation of a six-transistor SRAM memory cell, as shown in FIG. 2A, a predetermined information is frequently stored on the first memory node 102 , and information complementary thereto is stored on the second memory node 103 . Although it is not absolutely necessary for information to be stored to be stored directly and additionally as complementary, that is to say redundantly, in practice this is often carried out in such a way as to achieve particularly high reliability of the stored information and to increase the error robustness of the SRAM. To ensure memory cell. If, for example, the first memory node 102 is brought to a "high" electrical potential, then this electrical potential is applied to the gate terminals of the second flip-flop transistor 202 and the fourth flip-flop transistor 204 . Since the second flip-flop transistor 202 is a p-MOS transistor, in this operating state, the second flip-flop transistor 202 is non-conductive, whereas formed as n-MOS transistor fourth flip-flop transistor 204 is conductive. Simultaneously, the second electrical memory node 103 is brought to a "low" electrical potential (ie lower than the "high" electrical potential "), so that the gate terminal of the first flip-flop coupled to the second memory node 103 Transistor 201 , which is formed as a p-type MOS transistor, is electrically conductive, whereas the coupled to the second memory node 103 gate terminal of the third flip-flop transistor 203 , which is formed as an n-type MOS transistor blocks Due to the described conductivity states of the first to fourth flip-flop transistors 201 to 204 , the first memory node 102 is coupled via the first flip-flop transistor 201 to the electrical potential V _DD 107 of the supply voltage source, whereas to the second memory Node 103 is applied via the conductive fourth flip-flop transistor 204, the electrical ground potential V _SS 108. If the electrical potential at the word line 221 is turned off, s o that the first and second switching transistors 205 , 206 become electrically non-conductive, the impressed information is permanently stored in the first memory node 102 and as complementary information in the second memory node 103 .

To read this information, an electrical signal is applied to the word line 221 such that the first and second switching transistors 205 , 206 become conductive. As a result, such an electric current flows from the first memory node 102 into the first bit line 219 that is characteristic for the state of charge and for the stored information of the first memory node 102 . Analogously, from the second memory node 103 via the second switching transistor 206 into the second bit line 220 , such an electrical current is characteristic of the information stored in the second memory node 103 .

However, the information stored in the first and second memory nodes 102 , 103 is lost when the power supply voltage V _DD 107 is turned off. Before information is lost, as will be described later, the circuit arrangement 200 is protected.

Before switching off the supply voltage 107 , the information programmed in the SRAM memory cell 101 can be buffered in the latch circuit 104 .

This is done according to the invention by caching information programmed into the SRAM memory cell 101 in the latch circuit 104 by providing a first electrical potential on which the first memory node 102 is located to the nonvolatile memory cell 105 coupled thereto the first non-volatile memory cell 105 is thereby permanently brought into a first state of charge. In addition, the information programmed into the SRAM memory cell 101 is latched in the latch circuit 104 by providing a second electric potential on which the second memory node 103 is located to the second nonvolatile memory cell 106 coupled therewith second nonvolatile memory cell 106 is thereby permanently brought into a second state of charge.

In this backup phase, the SRAM memory cell 101 is no longer described with information, that is, no electrical signal is applied to the word line 221 . In this operating state, the potential V _{REW of} the first control voltage 216 is still at a logical value "0", whereas the electric potential V _{PRO of} the second control voltage 217 is brought to a logical value "1". As a result, the first side gate electrode 210 and the second side gate electrode 213 are brought to such an electrical potential that the first PLED layer sequence 209 and the second PLED layer sequence 212 allow a current flow in the horizontal direction according to FIG. 2A such that the information or charge stored in the first memory node 102 flows through the first PLED layer sequence 209 to a first latch node 224 that is coupled to the gate terminal of the first PLED memory cell transistor 208 . Analogously, the information stored on the second memory node 103 flows through the electrically conductive second PLED layer sequence 212 to a second latch node 225 , which is coupled to the gate terminal of the second PLED memory cell transistor 211 . Meanwhile, a feedback is interrupted because the electric potential V _{REW of} the first control voltage 216 is at a logical value "0". In this operating state, further, the electric potential V _{ACT of} the third control voltage 218 is at a logical value "0".

When the information / complementary information previously stored on the first and second memory nodes 102 , 103 is latched onto the first and second latch nodes 224 , 225, respectively, the power saving mode may be initiated. For this purpose, the supply voltage source is switched off, and the signal of the second control voltage 217 is brought to a logic value "0", whereby at the first and second side electrodes 210 , 213, the electrical potential is set so that the first PLED- Layer sequence 209 and the second PLED layer sequence 212 are electrically non-conductive. This prevents the charge stored in the first or the second buffer node 224 , 225 from flowing away. In this operating state, the SRAM memory cell 101 is switched off, and the information is stored permanently, that is to say clearly with a sufficiently high hold time, on the first or second buffer node 224 , 225 of the nonvolatile memory cells 105 , 106 .

In this energy-saving mode, also called power-down mode, all electrical signals are deactivated. The data is stored permanently on the internal PLED memory cells 105 , 106 . The SRAM memory cell 101 does not consume any power loss since there are no potential differences at its node.

In a further method step according to the method for operating the circuit arrangement 200 , the information temporarily stored in the latch circuit 104 is programmed back into the SRAM memory 101 .

The reprogramming of the information cached in the latch circuit 104 into the SRAM memory 101 is performed by bringing the first memory node 102 to the electric potential on which the first memory node 102 is using the state of charge of the first nonvolatile memory cell 105 prior to caching the information programmed in the SRAM memory cell 101 into the latch circuit 104 , and by using the state of charge of the second nonvolatile memory cell 106, the second memory node 103 is brought to the electric potential on which the second memory node 103 was prior to caching the information programmed in SRAM memory cell 101 into latching circuit 104 . By the state of charge is meant the electrical charge stored on the first and second latch nodes 224 and 225, respectively.

The writing back of the data from the nonvolatile PLED memory cells 105 , 106 begins with the reactivation of the supply voltage V _DD 107 of the SRAM memory cell 104 . Since the information stored on the first latch node 224 and the one on the second latch node 225 is complementary to each other, either the first PLED memory cell transistor 208 or the second PLED memory cell transistor 211 is electrically conductive in accordance with the stored information. The activation of a write-back signal V _REW places the first and second control transistors 214 , 215 in a conductive state and couples between the electrical potential of the third control voltage 218 and one of the two memory nodes 102 or 103 , as the case may be which information is cached in the nonvolatile memory cells 105 , 106 . By selecting a corresponding electrical potential V _ACT as a third control voltage 218 , the voltage between the two source / drain terminals of the respectively opened transistor 208 or 211 can be set so that the unbalance at the memory node 102 , 103 of the SRAM Memory cell 101 is sufficiently high and the write back takes place with an amplified signal. Ideally, the setting of the SRAM flip-flop (formed from the four flip-flop transistors 201 to 204 ) takes place on the rising edge of the reactivated supply voltage V _DD 107 . Since the program voltage V _{PRO of} the second control voltage 217 is at a logical value "0", the memory contents of the nonvolatile memory cells 105 , 106 are maintained, so that lossless information is stored. If the information stored in the SRAM memory cell 101 does not change over several process cycles, only the portion of the lost charge components on the PLED latch nodes 224 or 225, which is negligible for the power loss balance, is added in successive cycles.

Hereinafter, referring to FIG. 2B, a perspective view of a practical realization of the circuit arrangement 200 shown in FIG. 2A will be described. Corresponding elements are provided in Fig. 2B with the same reference numerals as in Fig. 2A. It should be noted that in FIG. 2B, for the sake of clarity, electrically insulating portions which cause mechanical stabilization and electrical decoupling of the electrically conductive components of the integrated circuit circuit arrangement 200 from each other are not shown.

Due to the superimposed representation of the individual components of the circuit arrangement 200 of FIG. 2B, the exact structure and coupling of the transistors 201 to 206 , 208 , 211 , 214 , 215 is not clearly apparent to each one of the transistors. Of establishing whether this regard to the remarks made with respect to a likewise designed as an integrated circuit another embodiment of the inventive circuit arrangement, which production method is described in connection with Fig. 3B to Fig. 3G.

In Fig. 2B, first and second coupling means 230 , 231 for electrically coupling the gate terminals of the first and second switching transistors 205 , 206 with the word line 221 are shown. The first coupling means 230 is made of polysilicon, whereas the second coupling means is made of a suitable metallic material. The components of the circuit arrangement 200 are formed on an electrically insulating silicon dioxide base layer 232 , which is deposited on a silicon substrate (not shown). An additional silicon layer (optionally also a silicide layer) is arranged on the silicon dioxide base layer 232 so that the silicon substrate, the silicon dioxide base layer 232 and the silicon arranged thereon have an SOI layer sequence ("silicon on insulator"). form. By means of structuring the upper silicon layer of the SOI layer sequence, a third coupling means 233 is formed, by means of which the second source / drain terminal 205 b of the first switching transistor 205 , the first source / drain terminal 203 a of the third flip -Flop- transistor 203 , the first source / drain terminal 201 a of the first flip-flop transistor 201 , and the first source / drain terminal 214 a of the first control transistor 214 are electrically coupled together. Furthermore, by means of the third coupling means 233, the first source / drain terminal 214 a of the first control transistor 214 is coupled to a mesa structure 234 . A mesa structure is a layer arrangement of a plurality of individual layers, in which island areas are structured by means of selective etching, so that integrated components are thereby formed. Referring to the circuit arrangement 200 , the first PLED layer sequence 209 and the second PLED layer sequence 212 are formed by means of the mesa structure 234 .

It should be noted that the first PLED memory cell transistor 208 and the second PLED memory cell transistor 211 according to the described embodiment are not formed as vertical transistors. As shown in FIG. 2B, the two source / drain terminals 208 a, 208 b of the first PLED memory cell transistor 208 are formed in surface areas of the mesa structure 234 . The gate terminal of the first PLED memory cell transistor 208 is arranged between the mesa structure 234 and the first PLED layer sequence 209 and between the source / drain terminals 208 a, 208 b and is not shown separately in FIG. 2B. Thus, referring to FIG. 2B, the channel region of the first PLED memory cell transistor 208 is horizontal. The same applies to the second PLED memory cell transistor 211 , of which only the second source / drain connection 211 b is shown in FIG. 2B, whereas the other components are concealed.

The first control transistor 214 is, as partially shown in FIG. 2B, formed as a kind of vertical transistor. As shown in Fig. 2B, the two source / drain terminals 214 a, 214 b are formed in different layer planes and are additionally offset in the horizontal direction against each other. By means of the third coupling means 233 , the first source / drain region 214 a is coupled to a left side wall of the mesa structure 234 according to FIG. 2B. A gate insulating layer is provided on the sidewall of the mesa structure 234 between the two source / drain terminals 214a , 214b . On the gate insulating layer, the gate terminal of the first control transistor 214 is laterally disposed (not shown), in coupling with a fifteenth coupling means 246 , by means of which the potential V _REW can be applied to the gate terminal of the first control transistor 214 is. Similarly, the second control transistor 215 , which is largely hidden in FIG. 2B, is formed.

The first source / drain terminal 208 a of the first PLED memory cell transistor 208 and the second source / drain terminal 214 b of the first control transistor 214 are formed integrally.

Furthermore, by means of a fourth coupling means 235, the second source / drain region 206 b of the second switching transistor 206 is connected to the first source / drain connection 204 a of the fourth flip-flop transistor 204 , to the first source / drain. Terminal 202 a of the second flip-flop transistor 202 and to the first source / drain terminal 215 a of the second control transistor 215 is coupled. Furthermore, a fifth coupling means 236 is shown in FIG. 2B, by means of which the first source / drain terminal 205 a of the first switching transistor 205 is coupled to the first bit line 219 . The first source / drain terminal 206 a of the second switching transistor 206 is coupled to the second bit line 220 by means of a sixth coupling means 237 . By means of a seventh coupling means 238 of polysilicon are the gate terminal of the third flip-flop transistor 203 , the gate terminal of the first flip-flop transistor 201 and the second source / drain terminal 206 b of the second switching transistor 206th coupled. By means of an eighth coupling means 239 , the gate terminals of the second flip-flop transistor 202 and the fourth flip-flop transistor 204 are coupled to each other and to the second source / drain terminal 205 b of the first switching transistor 205 . Furthermore, a ninth coupling means 240 is provided, by means of which the second source / drain terminal 203 b of the third flip-flop transistor 203 and the second source / drain terminal 204 b of the fourth flip-flop transistor 204 are coupled together , And by means of which the ground potential 108 can be applied to said terminals. By means of a tenth coupling means 241 , the second source / drain terminals 201 b, 202 b of the first and second flip-flop transistors 201 , 202 are coupled together, and by means of the tenth coupling means 241 is connected to said terminals, the electrical potential V _DD the supply voltage 107 can be applied. Further, an eleventh coupling means 242 is provided, by means of which the first side electrode 210 and the second side electrode 213 are formed, the eleventh coupling means 242 of polysilicon material being coupled to a twelfth coupling means 243 of a metallic material, by means of which twelfth Coupling means 243, the side gate electrodes 210 , 213 with the voltage source for providing the second control voltage 217 is coupled.

Furthermore, the first PLED layer sequence 209 and the second PLED layer sequence 212 are shown in FIG. 2B. The first source / drain terminal 214 a of the first control transistor 214 is coupled via a thirteenth coupling means 244 to an end portion of the first PLED layer sequence 209 . Via a fourteenth coupling means 245 , which in FIG. 2B is largely hidden by the first bit line 219 and has a similar structure to the thirteenth coupling means 244 , the first source / drain terminal 215a of the second control transistor 215 is also shown an end portion of the second PLED layer sequence 212 is coupled. By means of the fifteenth polysilicon coupling means 246 and by means of a sixteenth coupling means 247 of a suitable metallic material, the gate terminals of the first control transistor 214 and the second control transistor 215 are coupled together and to both gate terminals that of the first control Voltage 216 provided potential applied. Further, by means of a seventeenth coupling means 248, the second source / drain terminal 208 b of the first PLED memory cell transistor 208 to the second source / drain terminal 211 b of the second PLED memory cell transistor 211 is coupled, and it is the electrical potential of the third control voltage 218 can be applied to said terminals. The mentioned coupling means are provided in Fig. 2A with reference numerals.

Hereinafter, referring to FIG. 2C, a layout plan view of the circuit arrangement 200 according to the implementation shown in FIG. 2C will be described. The same components are provided with the same reference numbers.

As shown in Fig. 2C, the extent of the circuit arrangement 200 in FIG. 2C horizontal direction 7 F, whereas the extent of the circuit arrangement 200 in FIG. 2C vertical direction is 11.5 F. This results in an area requirement of the circuit arrangement 200 of 7 F × 11.5 F = 80.5 F ² .

In Fig. 2C, the n-MOS vertical transistors are shown as bars and the p-MOS vertical transistors as double bars. First polysilicon elements 250 and second polysilicon elements 260 are defined in the legend of FIG. 2C. Further, silicide regions in the legend of Fig. 2C are designated by reference numeral 270 . Moreover, in the legend of FIG. 2C, the representation of the mesa structures 234 is defined. Metal contacts in a direction orthogonal to the plane of the paper of FIG. 2C are marked with crosses 280 , 281 , 282 . It should be noted that in the layout view of Fig. 2C, in particular, the fifteenth coupling means 246 formed by means of a self-aligning process is shown only schematically.

In summary, in the circuit arrangement 200, the advantages of a six-transistor SRAM cell 101 are combined with the advantages of a PLED permanent memory 104 , wherein an optimization of the cell structure and the layout is achieved, whereby a circuit arrangement with a rectangular base an area requirement of 80.5 F ^{2 is obtained} on the surface of a substrate. It should be noted that the fabrication of the vertical MOSFETs may not necessarily be performed according to the method described in [10], but also according to a compatible alternative method. The choice of the fabrication method of the vertical transistors of the nonvolatile memory cells of the latch circuit depends on which type of nonvolatile memory is used for the latch circuit of the circuit arrangement according to the invention. The forming can optionally take place before, after or in time simultaneously with the vertical transistors of the SRAM memory cell.

In the following, a circuit arrangement 300 according to a second exemplary embodiment of the invention will be described with reference to FIG. 3A. Such components, for which a corresponding element is provided in the circuit arrangements 100 and 200 as described above, are given the same reference numerals.

In the circuit arrangement 300 , the nonvolatile memory cells 105 , 106 are configured as "ferroelectric random access memory" (FRAM) cells. This is indicated in the latch circuit 104 of FIG. 3A in that the first and second non-volatile memory cells 105 , 106 are shown with the circuit symbol of a variable capacitance. The functionality of an FRAM memory cell is described above and is essentially based on that by applying a suitable electric field to a capacitor with a dielectric of a ferroelectric material, a permanent electric dipole moment of the ferroelectric dielectrics is generated and in this way the applied electric field is clear is "saved".

The SRAM memory cell 101 of the circuit arrangement 300 is the same as that of the circuit arrangement 200 . The coupling between the SRAM memory cell 101 and the latch circuit 104 is again effected by means of the first auxiliary node 222 and the second auxiliary node 223, respectively. The first auxiliary node 222 is coupled to the first source / drain terminal 301 a of a first control transistor 301 , whose second source / drain terminal 301 b is coupled to the second latch node 225 . The second latch node 225 is coupled to one terminal of the second nonvolatile memory cell 106 formed as a FRAM cell, that is, as a capacitor filled with a ferroelectric dielectric, at the other terminal of which the electrical ground potential V _SS 108 is applied. The second auxiliary node 223 is coupled to the first source / drain terminal 302 a of a second control transistor 302 , whose second source / drain terminal 302 b is coupled to the first latch node 224 . The first latch node 224 is coupled to one terminal of the first nonvolatile memory cell 105 configured as an FRAM memory cell, to whose other terminal the electrical ground potential V _SS 108 is applied. A first control voltage V _RW 303 is coupled to the gate terminals of the first and second control transistors 302 .

The functionality of the circuit arrangement 300 will be described below insofar as it deviates from the functionality of the circuit arrangement 200 according to the first exemplary embodiment.

The programming, reading and erasing of information in the FRAM memory cell 101 is done as described above.

In order to initiate the low power mode having the above-described characteristics, the information stored in the first memory node 102 or the information complementary thereto stored in the second memory node 103 becomes the first latch node 224 and the second latch node, respectively 225 cached . It should be noted that the first and second nonvolatile memory cells 105 , 106 formed as FRAM memory cells are each formed as stacked capacitors formed in or on the substrate. In order to buffer the information stored in the memory nodes 102 , 103 into the FRAM memory cells 105 , 106 , the two transistor transistors 301 formed as n-MOS transistors are switched off before the supply voltage V _DD 107 of the SRAM memory cell 101 is switched off . 302 is brought into a conductive state by setting the first control voltage 303 appropriately. As a result, a current flow, ie a transport of electrical charge carriers from the first memory node 102 through the second control transistor 302 to the first latch node 224 or to the top terminal of FIG. 3A as the FRAM capacitor formed nonvolatile memory cell 105th allows. Furthermore, equalization of the electrical charge between the second memory node 103 by the first control transistor 301 to the second latch node 225 and to the upper terminal of the non-volatile memory cell 106 designed as an FRAM capacitor according to FIG. 3A is made possible. Clearly, the magnitude and sign of the permanent electric dipole moment of the ferroelectric dielectric of the FRAM capacitor 105 or 106 is a characteristic measure of the electrical charge carriers previously applied to the associated memory node 102 or 103 . Therefore, the information of the first and second memory nodes 102 , 103 is temporarily stored in the nonvolatile memory cells 105, 106, respectively.

In the described operating state, the information previously programmed into the memory nodes 102 , 103 is transferred to the latch nodes 225 , 224 and latched there, and after switching off the electrical potential V _{RW of} the first control voltage 303 , the electrical supply voltage V _DD 107 are switched off. In this state, no power dissipated and the information is stored in the latch circuit 104 permanently.

Before the start of the write-back phase, the control transistors 301 , 302 are brought back into a conductive state by setting a corresponding electrical signal as the first control voltage 303 . Then the potential V _{DD of} the supply voltage 107 is turned on. During the rising edge of the electrical potential V _DD 107 of the supply voltage source, the unequal FRAM capacitances (due to the different electrical dipole moments of the ferroelectric layers therein) cause a stronger or weaker coupling of the first node 102 and the second node 103 to the ground electrical potential V _SS 108 corresponding to the different conductivity states of the third and fourth flip-flop transistors 203 , 204 . This results in an unbalance of the electric charge at the first memory node 102 and at the second memory node 103 according to the information previously stored at these nodes. As a result, the six-transistor SRAM memory cell 101 is returned to the original state once V _{DD has reached} the full voltage swing.

As can be seen from the simple structure of the circuit arrangement 300 , in a design of the non-volatile memory cells as FRAM memory cells, a less complicated circuit architecture is achieved. It should be noted that the described memory cell can also be realized without the first control transistor 301 and the second control transistor 302 . In such a case, a circuit can be achieved with very little effort. An advantage of using control transistors 301 , 302 is that, in normal SRAM operation, secure electrical isolation of the SRAM memory cell 101 from the latch circuit 104 is realized, resulting in reduced capacitances at the first memory node 102 and the second memory node 103 . Therefore, the write and read times are shorter in the normal SRAM operation, since only the gate / drain capacitances of the first and second control transistors 301 , 302 are effective. In a circuit arrangement without control transistors 301 , 302 , the full FRAM capacitance would always be effective. It should also be noted that due to the stacked capacitor arrangement of the FRAM memory cells 105 , 106 an area-efficient implementation is ensured.

Furthermore, 3B, referring to Fig. 3G described to Fig., A method for producing a layer-assembly 300 of the above reference. Represents a realization to Figure 3A diagram described.

In order to obtain the layer sequence 310 shown in FIG. 3B, an SOI substrate is first produced. For this purpose, a silicon dioxide layer is deposited on a silicon substrate (not shown in FIG. 3B) and another silicon layer (or alternatively a silicide layer) is deposited on this silicon dioxide layer. This results in an SOI layer sequence ("silicon on insulator"), which is subsequently structured using a lithography and an etching process. By means of structuring the SOI layer sequence, first of all a rectangular, electrically insulating base 311 of silicon dioxide material is obtained, which is shown in FIG. 3B. The upper silicon layer disposed on the rectangular electrically insulating silicon dioxide base layer 311 is patterned to thereby form a first electrical coupling means 314 and a second electrical coupling means 315 . On or in the thus obtained first and second coupling means 314 , 315 , the transistors 201 to 206 , 301 , 302 of the circuit arrangement 300 are formed as vertical transistors.

It should be noted that in addition to the layer sequence 310 in FIG. 3B, a multiplicity of further vertical transistors (for example the further vertical transistor 312 ) belonging to further circuit arrangements which are shared with the circuit arrangement 300 are shown the substrate are formed, whereby a memory cell array is formed. The further vertical transistors are shown in FIG. 3B to represent the principle of an arrangement of several circuit arrangements on a substrate, and a simplified representation in Fig. 3C are not shown to Fig. 3G for the purpose.

In the following, the structure of the further vertical transistor 312 will be described by way of example with reference to FIG. 3B. Each of the vertical transistors of the circuit arrangement 300 may be configured like the further vertical transistor 312 of FIG. 3B. The vertical transistor 312 has a first source / drain terminal 312 a and a second source / drain terminal 312 b, a first source / drain region 312 c, and a second source / drain region 312 d. Between the first source / drain region 312 c and the second source / drain region 312 d, an undoped intermediate layer 312 e made of a semiconductive material is arranged. In the vertical direction shown in FIG. 3B, the layer arrangement of the first source / drain region 312 c, the intermediate layer 312 e and the second source / drain region 312 d is encased with a thin gate-insulating layer along the circumferential surface (not shown in Fig. 3B), and this gate insulating layer is covered by a gate electrode (not shown in Fig. 3B). By applying a suitable electrical voltage to the gate electrode, a conductive channel is produced in the intermediate layer 312 e, so that the layer arrangement 312 from FIG. 3B fulfills the functionality of a field-effect transistor whose conductive channel is more vertical in FIG. 3B Direction runs.

Further, as shown in FIG. 3B, the vertical transistors 201 to 206 , 301 , 302 are formed on the rectangular electrically insulating base 311 . According to the circuit diagram of FIG. 3A, the first source / drain terminal 201 a of the first flip-flop transistor 201 , the first source / drain terminal 203 a of the third flip-flop transistor 203 , the first source / Drain terminal 302 a of the second control transistor 302 and the second source / drain terminal 205 b of the first switching transistor 205 coupled by means of the second coupling means 315 of silicide material. Further, the first source / drain terminal 202 a of the second flip-flop transistor 202 , the first source / drain terminal 204 a of the fourth flip-flop transistor 204 , the first source / drain terminal 301 a of the first control transistor 301 and the second source / drain terminal 206 b of the second switching transistor 206 are coupled by means of the first coupling means 314 . Further shown in FIG. 3B are further vertical transistors 312 of circuit arrangements which are not associated with the circuit arrangement 300 .

In order to obtain the layer sequence 320 shown in FIG. 3C, a third coupling means 321 of polysilicon material is deposited such that thereby the gate terminals of the first and the second switching transistor 205 , 206 are coupled. Further, a fourth coupling means 322 is deposited, whereby the gate terminals of the first and second control transistors 301 , 302 are coupled together. In addition, a fifth coupling means 323 is deposited, whereby the gate terminals of the first and the third flip-flop transistor 201 , 203 are coupled, and further comprising said gate terminals with the first source / drain terminal 202 a of second flip-flop transistor 202 are coupled. Moreover, a sixth coupling means 324 , also of polysilicon material, is deposited on the layer sequence such that thereby the gate terminals of the second and fourth flip-flop transistors 202 , 204 are coupled together, and further comprising said gate terminals be coupled to the first source / drain region 203 a of the third flip-flop transistor 203 .

In order to obtain the layer sequence 330 shown in FIG. 3D, a first and a second stacked capacitor 331 , 332 are formed. Each of these stack capacitors has two electrically conductive capacitor elements (illustratively the analog to capacitor plates in macroscopic capacitors) and a ferroelectric dielectric layer (eg, lead zirconate titanate, Pb (Zr _{1 -x} Ti _x ) interposed therebetween. O ₃ , PZT). In other words, the first and the second stacked capacitors 331 , 332 form the two SRAM memory cells 105 , 106 . As shown in FIG. 3D, the first stacked capacitor 331 is coupled to the second source / drain terminal 302 b of the second switching transistor 302 , and the second stacked capacitor 332 is connected to the second source / drain. Terminal 301 b of the first control transistor 301 is coupled.

In order to obtain the layer sequence 340 shown in FIG. 3E, a seventh coupling means 341 is deposited on the first source / drain terminal 206 a of the second switching transistor 206 . Further, an eighth coupling means 342 is deposited on a portion of the third coupling means 321 . In addition, a ninth coupling means 343 on the first source / drain terminal 205 a of the first switching transistor 205 is discontinued. A tenth coupling means 344 is deposited on a portion of the fourth coupling means 322 . An eleventh coupling means 345 is deposited in the manner shown in FIG. 3E and connected to the second source / drain terminal 203 b of the third flip-flop transistor 203 , to the second source / drain terminal 204 b of the fourth flip-flop 203 b. Flop transistor 204 and with the according to FIG. 3E respectively upper electrically conductive capacitor elements of the first and second stacked capacitor 331 , 332 coupled. By means of the eleventh coupling means 345 , in each case the electrical ground potential V _SS can be applied to the four components mentioned (see FIG . Further, a twelfth coupling means 346 is deposited on the layer sequence such that thereby an electrical coupling between the second source / drain terminal 202 b of the second flip-flop transistor 202 and the second source / drain terminal 201 b of the first flip -Flop transistor 201 is realized.

In order to obtain the layer sequence 350 shown in FIG. 3F, the first bit line 219 is formed to be coupled to the ninth coupling means 341 . Further, the second bit line 220 is formed to be electrically coupled to the seventh coupling means 341 . Moreover, a thirteenth coupling means 351 is formed on the eighth coupling means 342 , and a fourteenth coupling means 352 is formed on the tenth coupling means 344 .

In order to obtain the circuit arrangement 300 shown in FIG. 3G, the word line 221 is formed on the thirteenth coupling means 351 and a fifteenth coupling means 360 is deposited on the fourteenth coupling means 352 , the electric potential being determined by means of the fifteenth coupling means 360 V _{RW can be applied} to the gate terminals of the first and second control transistors 301 , 302 .

In Fig. 3G an integrated circuit arrangement 300 is shown as realization of the circuit diagram of Fig. 3A. The coupling elements of FIG. 3G, which correspond to a connecting line shown in FIG. 3A, are identified there by the corresponding reference numeral.

In Fig. 3H, a layout plan view of the circuit arrangement 300 is shown, which corresponds to the perspective view of Fig. 3G.

The transistors and lines are given the same reference numerals in FIG. 3H as in FIG. 3G. In particular, reference is made to the legend of FIG. 3H, in which the area extent of the circuit arrangement 300 can be seen as an outline 370 . Further, the polysilicon elements 371 are shown in the legend, by means of which in particular the coupling between gate terminals of the transistors involved in the in Fig. 3A, Fig. Manner shown 3G are realized. Silicide elements 372 are further shown in the legend, by means of which in particular the source / drain terminals of the transistors involved are coupled together. Further, first, second and third metal contacts 373 , 374 , 375 are shown which effect respective electrical couplings in the direction perpendicular to the paper plane of Fig. 3H in the manner shown therein. Also shown in FIG. 3H are the word line 221 , the bit lines 219 , 220 and those lines 360 , 345 , 346 , by which the electrical potentials V _RW , V _SS and V _{DD are applied} to the respective terminals of the components of the circuit Arrangement 300 are created.

Hereinafter, referring to FIG. 4, a circuit arrangement 400 according to a third embodiment of the invention will be described.

The SRAM memory cell 101 of the circuit arrangement 400 is designed in the same way as the SRAM memory cell 101 of the circuit arrangement 200 . Therefore, structure and functionality of the SRAM memory cell 101 will not be described in detail below.

However, the latch circuit 104 is the circuit arrangement 400 otherwise constructed as in the embodiments described above, such that the latch circuit 104 of the circuit arrangement 400 includes two MRAM memory cells ( "magnetic random access memory"). Illustratively, an MRAM memory cell is a variable ohmic resistor which, as described above, often consists of two ferromagnetic layers separated by a tunnel layer. The ohmic resistance of such a layer arrangement is higher if the two ferromagnetic layers have mutually antiparallel magnetization directions than in the case of mutually parallel magnetization directions of both ferromagnetic layers.

The first auxiliary node 222 is coupled to the MRAM memory cell configured second non-volatile memory cell 106 , which is further coupled to the first source / drain terminal 401 a of a first control transistor 401 . The second source / drain terminal 401 b of the first control transistor 401 is coupled to the first source / drain terminal 402 a of a second control transistor 402 . At the second source / drain terminal 402 b of the second control transistor 402 , the electrical ground potential V _SS 108 is applied. In contrast, the gate terminal of the second control transistor 402 is coupled to the supply voltage V _DD . Further, the second source / drain terminal 401 b of the second control transistor 401 is coupled to the second source / drain terminal 403 b of a third control transistor 403 , whose first source / drain terminal 403 a with the also is coupled as a MRAM memory cell formed first nonvolatile memory cell 105 . The first nonvolatile memory cell 105 is further coupled to the second auxiliary node 223 . A first control voltage 404 is applied to the gate terminals of the first and third control transistors 401 , 403 . Furthermore, the _latch circuit 104 has a fourth control transistor 405 , to whose gate terminal a second control voltage V _PRO1 406 is applied. To the first source / drain terminal 405 a of the fourth control transistor 405 , the electrical potential V _DD 107 of the supply voltage source is applied. The second source / drain terminal 405 b of the fourth control transistor 405 is coupled to the variable resistors R ₁ and R _{2 of} the second and first non-volatile memory cells 106 and 105 , respectively, such that, given a predetermined current flow through the fourth control transistor. Transistor 405, the electrical resistance of the variable resistors R ₁ and R _{2 of} the second and first non-volatile memory cell 106 , 105 can be set to a predetermined value. Furthermore, the latch circuit 104 has a fifth control transistor 407 , at the first source / drain terminal 407 a, the potential V _DD 107 of the electrical supply voltage source is applied, and its gate terminal to the first auxiliary electric node 222nd is coupled. The second source / drain terminal 407 b of the fifth control transistor 407 is connected to the second source / drain terminal 408 b of a sixth control transistor 408 and to the first source / drain terminal 409 a of a seventh control transistor. Transistor 409 coupled. To the first source / drain terminal 408 a of the sixth control transistor 408 , the electrical ground potential V _SS 107 is applied. The gate terminal of the sixth control transistor 408 is coupled to the first auxiliary node 222 . To the gate terminal of the seventh control transistor 409 , a third control voltage V _PRO2 410 is applied. The second source / drain terminal 409 b of the seventh control transistor 409 is b with both the second source / drain terminal 411 b of an eighth control transistor 411 and to the second source / drain terminal 412 of a ninth Control transistor 412 coupled.

It should be noted that the fifth control transistor 407 and the eighth control transistor 411 are formed as p-type field-effect transistors, whereas all the other control transistors of the latch circuit 104 are formed as n-type field-effect transistors ,

The gate terminals of the eighth and ninth control transistors 411 , 412 are coupled to the second auxiliary node 223 , and to the first source / drain terminal 411 a of the eighth spike transistor 411 , the electrical potential V _DD 107 of the supply voltage source is applied , To the first source / drain terminal 412 a of the ninth control transistor 412 , the electrical ground potential V _SS 108 is applied.

The functionality of the circuit arrangement 400 will be described below.

In particular, in an operating state in which only the SRAM memory cell 101 is to be operated (for example, for reading or programming information), the first and third control transistors 401 , 403 are nonconductive, by appropriately setting the value of the first control voltage 404 is set.

If it is intended to switch to a low-power mode (power-down mode), the information stored on the first memory node 102 or the inverse information stored on the second memory node 103 must be buffered in the latch circuit 104 . For this purpose, first the two MRAM memory cells used as nonvolatile memory elements 105 , 106 , that is to say the variable resistors R ₁ , R ₂ , are brought to a defined output state by applying a suitable potential to the gate terminal of the fourth control transistor 405 this is brought into a conductive state. Then, a current I _{WR flows} , whereby the resistors R ₁ and R _{2 are brought} to a defined initial state. In other words, prior to the start of the power-down phase, a global write current is generated for all the circuit arrays 400 (ie, memory cells) of a memory cell array by means of an electrical signal having a logical value "1" of the second control voltage V _PRO1 406 . In this operating state, both the first control transistor 401 and the third control transistor 403 are non-conductive, which is realized by means of an electrical signal having the logic value "0" of the first control voltage 404 .

Now, as in the first memory node 102 stored information or stored in the second memory node 103 information in the variable resistors R ₁ and R ₂ encoded in the value of the respective ohmic resistor is latched. For example, in one scenario, the first memory node 102 is at a logical value "1", whereas the second memory node 103 is at a logical value "0". Now, consider the case that the seventh control transistor 409 is conductive, which is satisfied when an electrical signal having a logical value "1" is _applied to the gate terminal of the seventh control transistor 410 by means of the third control voltage 410 V _PRO2 "is created. In the considered scenario is coupled to the first storage node 102 coupled eighth control transistor 411, a p-MOS transistor non-conductive, since the first storage node is at the logic value "1" 102nd In contrast, the ninth control transistor 412 , an n-type MOS transistor, is conductive because its gate terminal is coupled to the first memory node 102 at the logical value "1". On the other hand, the second control node 103 is coupled at logic "0" to the gate terminals of the sixth control transistor 408 , an n-type MOS transistor, and the fifth control transistor 407 , a p-type MOS transistor. Since the second memory node is at a potential having a logic value of "0", the fifth p-MOS control transistor 407 is conductive, whereas the sixth n-MOS control transistor 408 is non-conductive. Due to the potential relationships described, a current flows from the first source / drain terminal 407 a of the fifth control transistor 407 located at the potential V _DD through the conductive fifth control transistor 407 , through the conductive seventh control transistor 409 and the conducting one ninth control transistor 412 , which is located at the electrical ground potential V _SS 108 , so that flows on the local current loop 413 as shown in FIG. 4, an electric current counterclockwise due to the potential difference between V _DD and V _SS . It should be emphasized that the direction of the electrical current flow on the local current loop 413 depends on whether the first memory node 102 or the second memory node 103 is at the logical value "1". If the conditions are reversed than in the described scenario, then in the current loop 413 a current flow according to FIG. 4 takes place in the clockwise direction. The current flow on the local current loop 413 generates a magnetic field as a function of its direction of rotation, the orientation of which is antiparallel to one another at the location of the first resistor R ₁ and at the location of the second resistor R ₂ . As a result, the soft magnetic ferromagnetic layer of the two MRAM memory cells 105 and 106 is oriented antiparallel to one another, so that in one of the MRAM memory cells 105 or 106, the resistance R ₁ or R ₂ assumes a higher value than in the other. Which resistor has the high and which resistor has the low electrical resistance depends on the orientation of the current flow on the local current loop 413 and therefore on the fact whether the first memory node 102 or the second memory node 103 is at a logic value " 1 "is. In other words, the information is stored in the form of high or low resistance in R ₁ or R ₂ . The functionality is realized by the described interconnection of the fourth control transistor 405 , the fifth control transistor 407 , the eighth control transistor 411 and the ninth control transistor 412 . Depending on the value of the logic signal on the first memory node 102 and on the second memory node 103 , the current flows through the local current loop 413 left or right. The current flow on the local current loop 413 is not interrupted by the seventh control transistor 409 , since in the described operating state as the third control voltage 410 V _PRO2 an electrical signal with a logical value "1" is set.

After completion of this latching phase , the information previously stored on the memory node 102 , 103 and the information complementary thereto are stored on the resistors R ₁ and R ₂ , which are illustratively the latching nodes of the latching circuit 104 .

In the write-back phase, the different electrical resistance in R ₁ and R _{2 is} detected. For this purpose, an electrical potential with a logic value "1" is applied to the gate terminals of the first control transistor 401 and the third control transistor 403 by means of the first control voltage 404 , so that a predetermined electric current through the second control Transistor 402 is divided into the two branches with the first variable resistor R ₁ and the second variable resistor R ₂ according to the values of these resistors. In other words, this current is distributed asymmetrically to the branches of the circuit arrangement 400 , which are coupled to the first memory node 102 and to the second memory node 103, respectively. Thereby, the previously stored in the non-volatile memory cells 105 , 106 information is written back to the two memory nodes 102 , 103 , whereby the conductivity of the first to fourth flip-flop transistors 201 to 204 is characteristically influenced such that the cell in the before the write-back ruling steady state tilts. In other words, the memory nodes 102 , 103 are then again in the same state as before the buffering, ie the information is written back. The tilting of the SRAM memory cell 104 into the associated stable state occurs when V _DD 107 has reached the full voltage swing.

This document cites the following publications:
[1] Lage, C, Hayden, JD, Subramanian, C (1996) "Advanced SRAM Technology - The Race Between 4T and 6T Cells", IEDM 1996: 271-274
Widmann, D, Mader, H, Friedrich, H (1996) "Technology of highly integrated circuits", Chapter 8.4.3, Springer Verlag, Berlin, IBSN 3-540-59357-8
[3] Nakazato, K, Piotrowicz, PJA, Hasko, DG, Ahmed, H, Itoh, K (1997) "PLED - Planar Localized Electron Devices" IEDM 1997: 179-182
[4] Mizuta, H, Wagner, M, Nakazato, K (2001) "The Role of Tunneling Barriers in Phase-State Low Electron-Number Drive Transistors (PLED-TRs)", IEEE Transactions on Electron Devices 48 (6): 1103-1108
[5] Nakazato, K, Itoh, K, Ahmed, H, Mizuta, H, Kisu, T, Kato, M, Sakata, T (2000) "Phase-State Low Electron-number Drive Random Access Memory (PLEDM)" IEEE International Solid State Circuits Conference 8/2000
[6] Alexe, M, Harnagea, C, Hesse, D (2000) "Nano Engineering for Nonvolatile Ferroelectric Storage", Physical Sheets 56 (10/2000): 47-50
[7] Reiss, G et al. (1998) "Giant Magnetoresistance - Transfer to Application" Physical Sheets 4/98: 339-341
[8] Herdt, CE (1992) "Analysis, Measurement, and Simulation of Dynamic Write Inhibit in nvSRAM Cell", IEEE Transactions on Electron Devices, 39 (5): 1191-1196
[9] Miwa, T, Yamada, J, Koike, H, Toyoshima, H, Amanumqa, K, Kobayashi, S, Tatsumi, T, Maejima, Y, Hada, H, Kunio, T (2001) "NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors "IEEE Journal of Solid-State Circuits, 36 (3): 522-527
[10] EP 0,920,060 A2 Reference Signs List 100 circuit arrangement
101 SRAM memory cell
102 first memory node
103 second memory node
104 latch circuit
105 first nonvolatile memory cell
106 second nonvolatile memory cell
107 supply voltage
108 ground potential
200 circuit arrangement
201 first flip-flop transistor
201 a first source / drain terminal
201 b second source / drain terminal
202 second flip-flop transistor
202 a first source / drain terminal
202b second source / drain terminal
203 third flip-flop transistor
203 a first source / drain connection
203 b second source / drain terminal
204 fourth flip-flop transistor
204 a first source / drain terminal
204 b second source / drain terminal
205 first switching transistor
205 a first source / drain connection
205b second source / drain terminal
206 second switching transistor
206 a first source / drain terminal
206b second source / drain terminal
208 first PLED memory cell transistor
208 a first source / drain terminal
208b second source / drain terminal
209 first PLED layer sequence
210 first side electrode
211 second PLED memory cell transistor
211 a first source / drain terminal
211 b second source / drain connection
212 second PLED layer sequence
213 second side electrode
214 first control transistor
214 a first source / drain terminal
214b second source / drain terminal
215 second control transistor
215 a first source / drain terminal
215 b second source / drain connection
216 first control voltage
217 second control voltage
218 third control voltage
219 first bit line
220 second bit line
221 word pipe
222 first auxiliary node
223 second auxiliary node
224 first cache node
225 second cache node
230 first coupling agent
231 second coupling means
232 Silica basecoat
233 third coupling agent
234 mesa structure
235 fourth coupling agent
236 fifth coupling agent
237 sixth coupling agent
238 seventh coupling agent
239 eighth coupling agent
240 ninth coupling agent
241 tenth coupling agent
242 eleventh coupling agent
243 twelfth coupling agent
244 thirteenth coupling agent
245 fourteenth coupling agent
246 fifteenth coupling agent
247 sixteenth coupling agent
248 seventeenth coupling agent
250 first poly-silicon elements
260 second poly-silicon elements
270 silicide areas
280 first metal contacts
281 second metal contacts
282 third metal contacts
300 circuit arrangement
301 first control transistor
301 a first source / drain terminal
301 b second source / drain terminal
302 second control transistor
302 a first source / drain terminal
302 b second source / drain terminal
303 first control voltage
310 layer sequence
311 rectangular electrically insulating base layer
312 further vertical transistor
312 a first source / drain terminal
312 b second source / drain terminal
312 c first source / drain region
312 d second source / drain region
312 e Intermediate layer
313 vertical transistors
314 first coupling agent
315 second coupling means
320 layer sequence
321 third coupling agent
322 fourth coupling agent
323 fifth coupling agent
324 sixth coupling agent
330 layer sequence
331 first stack capacitor
332 second stack capacitor
340 layer sequence
341 seventh coupling agent
342 eighth coupling agent
343 ninth coupling agent
344 tenth coupling agent
345 eleventh coupling agent
346 twelfth coupling agent
350 layer sequence
351 thirteenth coupling agent
352 fourteenth coupling agent
360 fifteenth coupling agent
370 outline
371 polysilicon elements
372 silicide elements
373 first metal contacts
374 second metal contacts
375 third metal contacts
400 circuit arrangement
401 first control transistor
401 a first source / drain terminal
401 b second source / drain terminal
402 second control transistor
402 a first source / drain terminal
402b second source / drain terminal
403 third control transistor
403 a first source / drain connection
403 b second source / drain connection
404 first control voltage
405 fourth control transistor
405 a first source / drain terminal
405 b second source / drain terminal
406 second control voltage
407 fifth control transistor
407 a first source / drain connection
407 b second source / drain connection
408 sixth control transistor
408 a first source / drain terminal
408 b second source / drain connection
409 seventh control transistor
409 a first source / drain connection
409 b second source / drain connection
410 third control voltage
411 eighth control transistor
411 a first source / drain connection
411 b second source / drain terminal
412 ninth control transistor
412 a first source / drain connection
412 b second source / drain connection
413 local current loop

Claims (10)

1. Circuit arrangement
with an SRAM memory cell
with vertical transistors;
with a first memory node, to which a signal can be applied, and with a second memory node, to which the inverse signal can be applied;
with a latch circuit
a first nonvolatile memory cell connectable to the first memory node;
a second nonvolatile memory cell which is coupleable to the second memory node;
which is set up so that in one
first operating state
a first electrical potential on which one of the memory nodes is located is provided to the nonvolatile memory cell coupled thereto, thereby permanently bringing this nonvolatile memory cell into a first physical state,
a second electrical potential on which the other of the memory nodes is located is provided to the other nonvolatile memory cell coupled thereto so as to permanently bring this nonvolatile memory cell into a second physical state;
second operating state
using the physical state of the first non-volatile memory cell, the first memory node is brought to the electrical potential on which it was in the first operating state;
using the physical state of the second nonvolatile memory cell, the second memory node is brought to the electrical potential at which it was in the first operating state. 2. Circuit arrangement according to claim 1, at least one of the nonvolatile memory cells has at least one vertical transistor. 3. Circuit arrangement according to claim 1 or 2, wherein the SRAM memory cell has six transistors. 4. Circuit arrangement according to claim 2 or 3, in which the vertical transistors of the memory cells a rectangular base are formed. 5. Circuit arrangement according to one of claims 1 to 4, wherein the at least a part of the transistors
Field effect transistors or
Bipolar transistors
are. 6. Circuit arrangement according to one of claims 1 to 5, at the first electric potential a Supply voltage and at the second electrical Potential is the ground potential. 7. Circuit arrangement according to one of claims 1 to 6, wherein the at least one of the non-volatile memory cells
a PLED memory cell
an EEPROM memory cell
an MRAM memory cell or
a FRAM memory cell
is. 8. A method of operating a circuit arrangement
with a circuit arrangement
with an SRAM memory cell
with vertical transistors;
with a first memory node, to which a signal can be applied, and with a second memory node, to which the signal inverse thereto can be applied;
with a latch circuit
a first nonvolatile memory cell connectable to the first memory node;
a second nonvolatile memory cell which is connectable to the second memory node;
which is set up so that in one
first operating state
a first electrical potential on which one of the memory nodes is located is provided to the nonvolatile memory cell coupled thereto, thereby permanently bringing this nonvolatile memory cell into a first physical state,
a second electric potential on which the other of the memory nodes is located is provided to the other nonvolatile memory cell coupled thereto so as to permanently bring this nonvolatile memory cell into a second physical state;
second operating state
using the physical state of the first non-volatile memory cell, the first memory node is brought to the electrical potential on which it was in the first operating state;
using the physical state of the second nonvolatile memory cell, the second memory node is brought to the electrical potential on which it was in the first operating state;
wherein according to the method
either programmed into the SRAM memory cell information, read or deleted; or
information programmed in the SRAM memory cell is latched in the latch circuit; or
the SRAM memory cell is turned off; or
in the latch circuit, cached information is reprogrammed into the SRAM memory cell. 9. The method according to claim 8,
in which information programmed into the SRAM memory cell is latched in the latch circuit by:
a first electrical potential on which one of the memory nodes is located is provided to the nonvolatile memory cell coupled thereto so as to permanently bring this nonvolatile memory cell into a first physical state;
a second electric potential on which the other of the memory nodes is located is provided to the other nonvolatile memory cell coupled thereto so as to permanently bring this nonvolatile memory cell into a second physical state. 10. The method according to claim 9,
wherein the information cached in the latch circuit is programmed back into the SRAM memory cell by:
using the physical state of the first non-volatile memory cell, bringing the first memory node to the electrical potential on which the first memory node was located prior to caching the information programmed in the SRAM memory cell into the latch circuit;
using the physical state of the second nonvolatile memory cell, the second memory node is brought to the electrical potential on which the second memory node was located prior to latching the information programmed in the SRAM memory cell into the latch circuit.