JPH01114072A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase stored charge and to improve soft error resistance due to alpha rays by forming a capacity element of a conductive film, which forms a high resistance element, and a conductive film of the upper layer so as to supply charge to a memory cell. CONSTITUTION:High resistance elements 7d, 7e, a power supply wire 7c and the lower part electrodes 7a and 7b of a capacity element are constituted by a conductive film of the third layer so as to be connected to the sources 3c and 3d of the transfer MOS transistors T3 and T4 through the connection holes 14a and 14b formed on an interlayer film 10 of a conductive film of the first and second layers, and on an interlayer insulating film 20 of the conductive films of the second and third layers so as to form a conductive film 15 and a capacity element of the fourth layer further through an insulating film 30. By this constitution, stored charge of a memory cell is increased and a soft error caused by alpha rays in company with micronization can be prevented from increasing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly to a static type M
The present invention relates to a semiconductor memory device that aims to miniaturize the memory cell area of an O3 random access memory and improve resistance to soft errors caused by alpha rays.

[Conventional technology]

The conventional flip-flop type static memory cell is 1
For example, as described in Japanese Patent Laid-Open No. 55-72069, it is composed of two high resistance elements and four n-channel MOS transistors. That is, as shown in the equivalent circuit in FIG. 9, a pair of drive MOS transistors T
1. Load resistors R1 and Rz are connected to each one of the drains of Ta, and T x .

The source of Ta is fixed at a predetermined potential (for example, ground potential), and the power supply voltage Vcc is applied to the other ends of Rt and Rz.
A small current is supplied to a flip-flop circuit consisting of Tll Tag Rut Rz. Furthermore, the storage nodes Nt and Nz of this flip-flop circuit have transfer Mo
S transistors Tδ and Ta are connected. Above 4
One transistor T x g T z @T8. A 1-bit cell is constituted by T4 and two load resistances Rt and Rz. Note that 1 is a word line, and 2a and 2b are data lines. Load resistance R1, R.

Generally, high-resistance polycrystalline silicon is used.

Next, the prior art will be explained in more detail using FIG. 10 and FIGS. 11(A) and 11(B). FIG. 10 shows a cross-sectional structure corresponding to the conventional example shown in FIG. 9. In FIG. 10, the gate electrodes 1a and lc of the MOS transistor are the first
The high-resistance element is constituted by a high-resistance portion 7e formed in a part of polycrystalline silicon, which is the second-layer conductive film. Both ends of the high resistance part 7e are made of low resistance polycrystalline silicon 7b, 7c, one of the low resistance polycrystalline silicon 7c is a power supply line for the power supply voltage Vcc, and the other end 7b is connected to the source diffusion ff3d of the transfer MOS transistor. It is connected.

11(A) and (B) show planar layout diagrams for one bit, (A) is a planar layout diagram of the transfer MOS transistor and drive MOS transistor, and (B)
) is a plan layout diagram of high-resistance polysilicon. In FIG. 11, word line 1a serves as a common gate for transfer MOS transistors Tδ and T4. Drain diffusion [3a, 3
Data lines 2a, 2b such as aluminum electrodes are connected to the terminals b through connection holes 4a, 4b. Furthermore, MOS
The sources 3 c v 3 d of the transistors Ts and Ta are connected to the gate electrode 1b of the driving MoS transistors Tx and Tz.
.

1c are directly connected through connection holes 5a and 5b.

Further, the sources of the drive MOS transistors Tx and Tz are connected to each other through a heavily doped n-type diffusion layer (n middle layer) 3f. The n layer 3f supplies the ground potential Vss to the sources of all drive MOS transistors in the memory. Furthermore, as shown in FIG. 11(B), a low resistance polycrystalline silicon 7
c is a memory cell (all high-resistance elements in the cell have a power supply voltage V
cc is supplied.

[Problem that the invention seeks to solve]

Next, the problems of the static memory cell of the above-mentioned conventional structure will be described.

(1) The n+ layer 3f used as a wiring for applying a ground potential to the source of the drive MOS transistor was a factor in increasing the vertical dimension of the memory cell. Furthermore, in the n+layer 3f, during memory operation, a current flows from the data line 2a in FIG. The problem was that a potential drop occurred. In order to solve this problem, it has conventionally been necessary to supply the ground potential to the n-middle layer using aluminum wiring at a rate of one every few cells, and this aluminum wiring increases the area of the entire memory chip.

2) When alpha rays, which are generated when trace amounts of uranium and thorium contained in ceramic materials, resin materials, and wiring materials used to seal memory chips decay, enter a memory cell, the range of the alpha rays decreases. Electron-hole pairs are generated along the storage nodes Nx, Nz, and are mixed with the charges stored in the storage nodes N1. The potential of Nt is varied, and as a result, information in the memory is destroyed. This is a phenomenon called a soft error. In conventional static memory, charge dissipation due to α rays is compensated for by the P-N junction capacitance formed between the drain region n of the drive MOS transistor/diffusion layer and the P-type silicon substrate and the insulating film capacitance by the gate oxide film. It was possible to accumulate an amount of charge. However, when the area of a memory cell is reduced, the accumulated charge becomes insufficient to compensate for the loss of charge due to α rays. Therefore, the conventional static memory cell structure has the problem that the soft error rate increases as the size becomes smaller, and the reliability of the memory decreases significantly.

(3) The electrical conductivity of the high-resistance polycrystalline silicon used for the load resistors Rz and Rz is determined by the interface states formed at the grain boundaries. Therefore, when using a film that traps a large amount of charge, such as a plasma nitride film, as a protective film for a memory cell, or when forming an electrode material such as an aluminum wiring, the height of the potential barrier at the grain boundary of high-resistance polycrystalline silicon is changes.

Therefore, there was a problem that the values of the load resistances R1 and Rz fluctuated.

(4) Data lines 2a, 2b and transfer MOS transistor T
The connection holes 4a and 4b connecting the drain diffusion layers 3a and 3b of the transfer MOS transistors Ta and the gate electrodes 1a of the transfer MOS transistors Ta and the gate electrodes 1a of the gate electrodes 1a of the transfer MOS transistors Ta and the gate electrodes 1a of the gate electrodes 1a and 1a of the transfer MOS transistors Ta and the connection holes 4a and 4b that connect the drain diffusion layers 3a and 3b of the transistors 3a and 3b are connected to each other, and it is necessary in terms of layout to secure an allowance for mask misalignment. This causes an increase in the vertical dimension of the memory cell, which poses a problem in reducing the area of the memory cell.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the prior art and to provide a static MOS random access memory device that requires a small area and has high resistance to soft errors caused by alpha rays.

[Means for solving problems]

The above object is to form a conductive film above the main surface of the semiconductor substrate for fixing the source of the drive MoS transistor to ground potential, and to connect the drain of the transfer MoS transistor and the data line of the storage device using the same layer as the conductive film. This is achieved by connecting the

Furthermore, the lower electrode of the capacitive element and the high resistance element are formed in the same layer, and the lower electrode of the capacitive element is connected to the storage node to supply charge to the memory cell, and the lower electrode of the capacitive element is fixed to an arbitrary voltage. This is achieved by covering the high resistance element with.

[Effect]

By forming the region connecting the source of the drive MOS transistor as a conductive film on the main surface of the semiconductor substrate, the region of the ground line can be eliminated. Also, transfer M in the same layer as the conductive film
By connecting the drain of the OS transistor and the data line of the storage device, the alignment margin between the gate of the transfer MOS transistor and the connection hole of the data line can be reduced. With the above, the area of the memory cell can be reduced.

Further, by forming a capacitive element with a conductive film forming a high resistance element and an upper conductive film, accumulated charge can be increased, and resistance to soft errors caused by α rays can be improved.

Furthermore, by covering the high resistance part with the upper conductive film forming the capacitive element and the conductive film forming the ground line, the electric field applied to the high resistance can be made constant, and the characteristics of the high resistance can be stabilized. .

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 8.

Embodiment 1 FIG. 1 is a cross-sectional structure of a static MOS memory showing a first embodiment of the present invention. In Figure 1, the first
A conductive film such as a polycrystalline silicon film, a metal silicide film, or a metal polycide film is used as the conductive film in the second layer, and the MO
They constitute the gate electrodes 1a and lc of the S transistor. Each transistor is electrically isolated by a silicon oxide film 8. The gate electrode 1c of the drive MOS transistor is connected to the source diffusion Jli13d of the transfer MOS transistor through a hole in which the gate oxide film 9 is partially etched.
connected directly to. The ground line 13c is formed using a conductive film such as a polycrystalline silicon film as a second layer conductive film, a metal silicide film, or a metal polycide film, and connects the source diffusion layer of the drive MOS transistor. Furthermore, a connection layer 1 formed of the same layer as the grounding line 13c
The drain diffusion layer 3b of the transfer MOS transistor and the data line 2b are connected via 3b. Further, the third layer conductive film is formed of polycrystalline silicon, and is formed in the high resistance element region 7e.
, has low resistance regions 7b and 7c, and the - end 7c is connected to the power supply line,
The other end 7b is a transfer MoS transistor via a connection hole,
It is connected to the second source diffusion layer 3d, and further forms a capacitive element with the fourth layer conductive film 15 via the insulating film 30. Here, the upper electrode 15 of the capacitive element is fixed at an arbitrary voltage such as ground potential or power supply voltage.

This will be explained in more detail using FIGS. 2(A) and 2(B).

Figure 2 is a plan layout diagram of this embodiment, and Figure 2 (
A) is a plan layout diagram of the first and second conductive films, and FIG. 2(B) is a plan layout diagram of the third and fourth conductive films and aluminum electrodes.
On the actual side of this book, as shown in Figures 2 (A) and (B),
Drive MOS transistors Ti, Tx sources 3g, 3h
are connected to each other by a second conductive film 13c via connection holes 12c and 12d formed in the interlayer insulating film 10 between the first and second conductive films.

Furthermore, the second layer conductive film 13c is fixed to the ground potential and connected to the sources of all drive MOS transistors in the memory device. In addition, the second layer conductive film 13a
, 13b is the connection hole 12a.

The second layer conductive films 13a, 13b are connected to the drains 3a, 3b of the transfer MoS transistors Ta, Tt through the connection hole 4a.

4b through the aluminum electrode 2a of the data line.

2b is connected.

The third layer of conductive film includes high resistance elements 7d and 7e, and power supply line 7c.
and the lower electrodes 7a and 7b of the capacitive element, and the interlayer insulating film 10 between the first and second conductive films and the interlayer insulating film 20 between the second and third conductive films. It is connected to the sources 3c and 3d of the transfer MOS transistors Tll and T4 through the formed connection holes 14a and 14b, and supplies a minute current.

Next, a method for manufacturing the memory cell of this embodiment will be explained in order of steps with reference to the cross-sectional view shown in FIG.

First, as shown in Figure 3 (A), the specific resistance is 5 to 20 Ω・c.
After forming a P-type well 16 with an impurity concentration IQ of 16 to 101δl-8 in an n-type silicon substrate 26 on the m(100) plane by boron ion implantation and thermal diffusion, LOCO
A silicon oxide film 8 with a thickness of 100 to 11,000 nm is formed using a method such as No.
A gate oxide film 9 of ~1100n is formed.

Next, as shown in FIG. 3(B), a connection hole 5b is formed in a part of the gate oxide film 9, and a conductive film such as polycrystalline silicon is deposited by a CVD method, and then a low resistance film is formed by a phosphorus treatment or the like. After that, an oxide film 21 is deposited by CVD method or the like, and gate electrodes 1a, lc are formed by photolithography and dry etching.
are formed, and ions such as arsenic are implanted using the gate electrodes 1a and lc as masks to form N-type impurity diffusion layers 3b,
form 3d.

Next, as shown in FIG. 3(C), a silicon oxide film or the like, which is the interlayer insulating film 10, is deposited to a thickness of 50 to 500 nm using a CVD method or the like.
A connection hole 12b is formed in the source diffusion layer of the driving MoS transistor and the drain diffusion layer 3b of the transfer MoS transistor, and the second layer conductive film, such as polycrystalline silicon or metal silicide film, is deposited using the CVD method. Alternatively, the ground line 13c and the connection layer 13b are formed by depositing by sputtering or the like, and after introducing N carved parts by phosphorus treatment or ion implantation, by photolithography and dry etching.

Next, as shown in FIG. 3(D), a silicon oxide film or the like, which is the first interlayer insulating film 20, is deposited to a thickness of 50 to 500 nm using a CVD method or the like.
m deposited and transfer MoS transistor source diffusion layer 3d
After forming a connection hole 14b on top for connecting the third layer conductive film, polycrystalline silicon is deposited to a thickness of 5 mm by CVD or the like.
After depositing 0 to 200 nm, patterning is performed by photolithography and dry etching, and then a high resistance part 7e is formed.
An n-type impurity such as arsenic is applied at a dose of 10 to both ends 7c and 7b of
xi to 10" is implanted to lower the resistance of the power supply line 7c and the lower electrode 7b of the capacitive element.

Next, as shown in FIG. 3(E), a silicon oxide film or the like is deposited to a thickness of 50 to 500 nm on the third conductive film by CVD or the like.
After depositing m, the insulating film on the capacitive element lower electrode 7b is removed, and the insulating film 30 for forming the capacitor is deposited by CVD or the like.
After ~50 nm deposition, the 41st! Polycrystalline silicon or the like, which is the Ith conductive film, is deposited to a thickness of 100 to 500 nm by CVD or the like, and after its resistance is lowered by phosphorus treatment or ion implantation, the capacitive element upper electrode 15 is formed by photoresist and dry etching. Here, in order to simplify the process, it is also possible to provide only the thin insulating film 30 for forming a capacitor between the third WI and fourth conductive films.

Next, as shown in FIG. 3(F), after depositing an interlayer insulating film 11 such as a phosphor glass film to a thickness of 100 to 11,060 nm, a connection hole 4b is opened on the connection M13b, and aluminum is
Aluminum electrode 2b is deposited to a thickness of 00 to 2000 nm and becomes a bit line by photolithography and dry etching.
form.

According to this embodiment, the amount of charge accumulated in the storage node can be increased, and soft errors caused by α rays can be reduced. Furthermore, by using a conductive film as the ground line, the area of the memory cell can be reduced. Furthermore, since the high-resistance element is covered with the fourth layer of conductive film, stable high-resistance characteristics can be obtained.

Embodiment 2 FIG. 4 shows a static type M showing a second embodiment of the present invention.
This is a cross-sectional structure of an OS memory. In FIG. 4, the first layer of conductive film is a conductive film such as a polycrystalline silicon film, a metal silicide film, or a metal polycide film, and the MOS
They constitute the gate electrodes 1a and lc of the transistor.

Each transistor is electrically isolated by a silicon oxide film 8. Drive MOS transistor gate 'R
Wa1c connects the source diffusion layer 3d of the transfer MOS transistor through a hole in which the gate oxide film 9 is partially etched.
connected directly to. The ground line 13c is formed using a conductive film such as a polycrystalline silicon film, a metal silicide film, or a metal polycide film, which is a second-layer conductive film, and connects the source diffusion layer of the driving MoS transistor. Furthermore, a connection layer 1 formed of the same layer as the grounding line 13c
The drain diffusion layer 13b of the transfer MOS transistor and the data line 2b are connected via 3b. Further, the third layer conductive film is formed of polycrystalline silicon, and includes high resistance regions 7e,
It has a low resistance region 7b, and the low resistance region 7b constitutes the lower electrode of the capacitive element and is connected to the transfer MOS through the connection hole.
It is 3D connected to the source diffusion layer of the transistor. The fourth layer of conductive film constituting the upper electrode 15 of the capacitive element is
It is fixed to the power supply voltage and also serves as a power supply line that supplies the power supply voltage to the high resistance region 7e through the connection hole.

This will be explained in more detail using FIGS. 5(A) and 5(B).

FIG. 5 is a plan layout diagram of this embodiment, and FIG.
A) is a plan layout diagram of the first and second layer conductive films, and FIG. 5(B) is a plan layout diagram of the third and fourth layer conductive films and aluminum electrodes. In this example, the planar layout, functions, etc. of the first and second layer conductive films and aluminum electrodes are the same as in the first example, and will therefore be omitted. The third layer conductive film is
High resistance elements 7d, 7e and lower electrode 7a of capacitive element,
7b and transfer Mo through the connection holes 14a and 14b.
S transistor T8. It is connected to Ta sources 3c and 3d and supplies a minute current. The upper electrode 15 of the capacitive element made of the fourth layer conductive film is fixed to the power supply voltage and also serves as a power supply line, and is connected to the high resistance part 7d through the connection holes 6a and 6b.
, 7e.

Next, the method for manufacturing the memory cell of this embodiment is shown in FIG.
The steps will be explained in order. Note that the steps up to the formation of the second layer conductive film are the same as those in the first embodiment, and will therefore be omitted.

First, as shown in FIG. 6(A), the grounding line 13c is connected to the second layer of conductive film.
After forming the connection layer 13b, a silicon oxide film, etc., which is the interlayer insulating film 20, is deposited to a thickness of 50 to 500 nm by CVD or the like.
Transfer MoS transistor source diffusion layer 3
Connection hole 14b for connecting the third layer conductive film on d
After opening a hole and depositing polycrystalline silicon, which is the third layer of conductive film, to a thickness of 50 to 200 nm by CVD or the like, patterning is performed by photolithography and dry etching, and then a region that will become the lower electrode of the capacitive element is formed. Arsenic is implanted into the region 7b at a dose of 101 to 10"Ql-" to form a high resistance region 7e and a low resistance region 7b.

Next, as shown in FIG. 6(B), after depositing an insulating film such as a silicon oxide film to a thickness of 50 to 500 nm by the mcVD method or the like, this insulating film on the capacitive element lower electrode 7b is photolithographically deposited. It is removed by wet etching, and then a thin insulating film 30 for forming a capacitor is etched by CVD or the like.
Deposit 50 nm. After that, a connection hole 6b for connecting the power supply line 15 to the high resistance part 7e is opened by photolithography and dry etching, and then polycrystalline silicon, which is a fourth layer of conductive film, is deposited by CVD or the like. The upper electrode (power line) 15 of the capacitive element is formed by photolithography and dry etching.

Here, in order to simplify the process, the interlayer insulating film between the third and fourth conductive films is a thin insulating film 30 for forming a capacitor.
It is also possible to do just that.

Next, as shown in FIG. 6(C), after depositing an interlayer insulating film 11 such as a phosphorus glass film to a thickness of 100 to 11,000 nm,
A connection hole 4b is opened on the connection layer 13b.

After depositing aluminum to a thickness of 500 to 2000 nm, an aluminum electrode 2b that will become a bit line is formed by photolithography and dry etching.

According to this embodiment, the dimensions of the high resistance element can be increased by about 20 to 30% compared to the first embodiment, and the resistance value of the high resistance element can be increased.

Embodiment 3 FIG. 7 is a cross-sectional structure of a static MOS memory showing a third embodiment of the present invention. In Figure 7, the first
The layer film is a conductive film such as a polycrystalline silicon film, a metal silicide film, or a metal polycide film.
They constitute the gate electrodes 1a and lc of the S transistor. Each transistor is electrically isolated by a silicon oxide film 8. The gate electrode 1c of the drive MOS transistor is directly connected to the source diffusion layer 3d of the transfer MOS transistor through a hole in which the gate oxide film 9 is partially etched. The ground line 13c is formed using a conductive film such as a polycrystalline silicon film, a metal silicide film, or a metal polycide film, which is a second-layer conductive film, and connects the source diffusion layer of the drive MOS transistor. . Further, the drain diffusion layer 3b of the transfer MOS transistor and the data a2b are connected through a connection layer 13b formed of the same layer as the ground line 13c. The third layer conductive film is made of polycrystalline silicon and has a high resistance region 7e and a low resistance region 7b. It is connected to the source diffusion layer 3d of the MoS transistor. The fourth layer of conductive film is the upper electrode 15a of the capacitive element and the power supply line 15.
The upper electrode 15a of the capacitive element is fixed to an arbitrary voltage such as the ground voltage, and the power line 15b is fixed to the power voltage and supplies the power voltage to the high resistance part 7e through the connection hole.

This will be explained in more detail using FIGS. 8(A) and 8(B).

FIG. 8 is a plan layout diagram of this embodiment, and FIG.
A) is a plan layout diagram of the first and second conductive films, and FIG. 8(B) is a plan layout diagram of the third and 41st conductive films and aluminum electrodes.
Planar layout diagram 1 of the first, second and third conductive films and aluminum electrodes in this example.
Functions and the like are the same as in the second embodiment.

The explanation will be omitted. The fourth layer of conductive film constitutes the upper electrode 15a of the capacitive element and the power line 15btt, and the power line 15b
are connected to high resistance parts 7d and 7e through connection holes 6a and 6b to supply power supply voltage.

The method for manufacturing the memory cell of this embodiment is omitted because it can be performed by master slicing the fourth layer conductive film in contrast to the second embodiment.

According to this example, as in Example 2, the dimensions of the high-resistance element can be made approximately 20 to 30% longer than in the example, and the upper electrode of the capacitive element can be set to an arbitrary voltage. .

〔Effect of the invention〕

According to the present invention, it is possible to achieve high integration, prevent an increase in the soft error rate caused by alpha rays due to miniaturization, and create a state-type MOS memory that has stable high-resistance element characteristics. It can be realized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the first embodiment of the present invention, FIG. 2 is a plan layout diagram of FIG. 1, FIG. 3 is a sectional view of the forming process of FIG. 1, and FIG. 5 is a plan layout diagram of FIG. 4, FIG. 6 is a sectional view of the forming process of FIG. 4, and FIG. 7 is a cross-sectional view of the embodiment of FIG. 3 of the present invention. The sectional view shown in FIG. 8 is the plan layout diagram of FIG. 7, and FIG.
The figure shows an equivalent circuit of a conventional static type MOS memory cell, FIG. 10 is a sectional view thereof, and FIG. 11 is a plan layout diagram of FIG. 1a to 1c...first layer conductive film, 2a, 2b...
Aluminum electrode, 38-3h...source or drain diffusion layer, 4a-4b, 5a-5c, 6a-6b, 1
2a-12d, 14a-14b-connection holes, 13a-13
b...Second layer conductive film, 7a-7e...Third layer conductive film, 15, 15a-15b...Fourth layer conductive film, 2b...N-type silicon substrate , 16th/[ii] 221 (A) (B) Heel home rule --→ ← ---17th rule ---3rd concave 3 Figure (ε) (F) No. 4I] Month 5fl H--l cell --H Dorl Cell → Otori # Birthing Hole 15 Den j1. @ Fig. 6 (A) (Q) 7 Fig. 8/Sb tJ practice 9 (21 Fig. 10/l Concave

Claims (1)

[Claims] 1. Two drive transistors constituting a flip-flop provided on the surface of a semiconductor substrate and a pair thereof;
In a static random access memory cell having two transfer transistors and two load elements, the first layer of conductive film forms the gate electrode of the active transistor, and the second layer of conductive film connects the source of the drive transistor to ground potential. The third conductive film forms a high resistance element and the lower electrode of the capacitive element, the lower part of the capacitive element is connected to the storage node, and the fourth conductive film forms the capacitive element. A semiconductor memory device characterized in that an upper electrode is formed. 2. Claim 1, characterized in that the fourth layer conductive film is fixed at an arbitrary voltage, and the power line that supplies the power voltage to the high resistance element is constituted by the third layer conductive film. 1. Semiconductor storage device described in Section 1. 3. The semiconductor memory device according to claim 1, wherein the fourth layer conductive film is fixed to a power supply voltage and constitutes a power supply line that supplies the power supply voltage to the high resistance element. 4. The fourth layer of conductive film constitutes the upper electrode of the capacitive element, and the upper electrode is fixed to an arbitrary voltage,
2. The semiconductor memory device according to claim 1, wherein a power supply line for supplying a power supply voltage to a high resistance element is formed in the same layer. 5. Claims characterized in that the second conductive film constituting the ground line is formed of the same layer as the conductive film connected to the drain of the transfer MOS transistor and the data line of the storage device. 2. The semiconductor memory device according to item 1.