JPH0279468A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance the reliability of element by furnishing an electroconductive layer approx. over the whole periphery of a resistance layer with an insulation film interposed, stabilizing the resistance value of a resistance layer as the load against possible resistance modulation caused by the potential of the surrounding conductive layer, and enhancing the resisting ability to software errors. CONSTITUTION:A non-doped polysilicon layer 22 as a resistance load R1 is formed on another polysilicon layer 16, which is provided on a semiconductor substrate 2 in the element region, with a silicon nitride film 18 interposed. Except contacting parts with polysilicon layers 16, 20, the whole peripheral surfaces of this polysilicon layer 22 are covered with another polysilicon layer 26 of protection plate with its voltage held constant through a silicon oxide film 24. Accordingly this is free from resistance modulation due to potentials of the low resistance polysilicon layer 16, 20 and an Al wiring layer 30 as electroconductive layers situated over and under the high resistance polysilicon layer 22. Also in the neighborhood of contacting parts with the non-doped polysilicon layers 22, 16 as a resistance load R1, a large capacitance is formed between the polysilicon layers 22, 26, so that the capacity of information storing node is increased and the resisting ability to software errors enhanced.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor memory device and a method for manufacturing the same, particularly an SRAM using a resistive layer as a load and a method for manufacturing the same. The purpose of this flip-flop is to provide a semiconductor memory device and its manufacturing method that can improve the reliability of the device by stabilizing the resistance value of the layer and increasing resistance to soft errors, and a method for manufacturing the same. In a semiconductor memory device having a type of memory cell, a conductive layer is provided on substantially the entire circumferential surface of the resistive layer with an insulating film interposed therebetween.

[Industrial Field of Application] The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a MOS type SRAM using a resistive layer as a load and a method of manufacturing the same.

[Prior art] In general, an M using a polysilicon resistance layer as a load element
As shown in FIG. 3, the OS type SRAM cell has 1
A pair of resistive loads R1, R2, a pair of driver transistors Tl, T2, and a pair of transfer transistors T
3. It is composed of T4.

That is, a resistive load R1 and a driver transistor T1 and a resistive load R2 and a driver transistor T2 are provided in parallel between the power supply voltage Vcc and the ground voltage Vllll. The information storage node A where the resistive load R1 is connected to the train of the driver transistor T1 and the information storage node B where the resistive load R2 and the drain of the driver transistor T2 are connected are the driver transistors T2. Connected to the gate of TI.

Further, transfer transistor T3. The sources of T4 are connected to the bit lines BL, BL, the gates are connected to the word line WL, and the drains are connected to the information storage nodes A, B, respectively.

In this way, since the SR and AM cells are composed of flip-flops, the driver transistor TI.

Either one of T2 is always on, and the resistive load R
1 and R2 from the power supply voltage VCC to the ground voltage ■. A current flows steadily through.

Each of the information storage nodes A and B has a parasitic capacitance C, and by continuing to charge this parasitic capacitance C via resistive loads R1 and R2, information storage is maintained.

A cross-sectional view of a conventional resistive load type SRAM cell is shown in FIG.

In the element region separated by the field oxide film 54 formed on the semiconductor substrate 52, n1 type impurity regions 56 and 58 serving as the source and drain regions of the transfer transistor T1 and ground voltage 8. connect to n
A + type impurity region 60 is formed.

A polysilicon layer 64 as the gate of the transfer transistor T1 is formed on the semiconductor substrate 52 sandwiched between the n1 type impurity regions 56 and 58 as the source and drain regions of the transfer transistor T3, with a gate oxide film 62 interposed therebetween. has been done. Further, this polysilicon layer 64 is connected to the word line WL.Similarly, a polysilicon layer 66 as the gate of the driver transistor T2 is formed on the semiconductor substrate 52 in the element region via a gate oxide J]i12. is formed.

This polysilicon layer 66 has an n+ type impurity region 5 serving as a drain region of the transfer transistor T3.
It is connected to 8.

Further, a non-doped polysilicon layer 70 as a resistive load R1 is formed on the polysilicon layer 66 via a silicon oxide film 68. This polysilicon layer 70 is
On one side, it is connected to polysilicon layer 66. On the other hand, impurities are introduced into a part of the polysilicon layer 70 above the n+ type impurity region 10 to lower the resistance, thereby forming a polysilicon layer 72 as a power supply layer connected to the power supply voltage VCC. .

Further, a PSGWA 74 as a glabellar insulating film is formed on the entire surface, and an aluminum<AI) wiring is connected to the n" type impurity region 56 as a source region of the transfer transistor T3 through a contact hole opened in this PSG film 74. A layer 76 is formed. This Aj wiring layer 76 is connected to the bit line BL.

In such a conventional SRAM cell, the resistive load R1
, R2 from the power supply voltage Vcc to the ground voltage V. Since the 'rIjh current flows steadily through the resistive loads R1 and R2, the power consumption of the element increases if the values of the resistive loads R1 and R2 are low. Therefore, it is required to increase the values of the resistive loads R1 and R2.

In order to meet these requirements, as shown in FIG.
8 and a polysilicon layer 80 as a power supply layer connected to the power supply voltage Vcc are separately provided, thereby reducing the thickness of the polysilicon layer 78 as the resistive load R1,
Its resistance value can be increased.

That is, a silicon oxide film 68 is formed on the polysilicon layer 66, and the power supply voltage VC is connected through the silicon oxide film 68 above the n'' type impurity region 10 which is connected to the ground voltages (2) and (s).
A polysilicon layer 80 is formed as a power supply layer connected to c. A silicon oxide film 82 is formed on this polysilicon layer 80 and silicon oxide film 68.

Then, the polysilicon layer 8 is formed on the polysilicon layer 66 via the silicon oxide film 68 and the silicon oxide film 82.
A non-doped polysilicon layer 78 serving as a resistive load R1 is formed on the silicon oxide film 82 via a silicon oxide film 82. This polysilicon layer 78 is thin and has a high resistance value, and is connected to the polysilicon layer 66 on one side and to the polysilicon layer 80 as a power supply layer on the other side.

In this way, by reducing the film thickness of the polysilicon layer 80 as a power supply layer connected to the power supply voltage cc and the polysilicon layer 78 as a resistive load R1 provided separately, the resistance value can be increased. This reduces the power consumption of the device.

[Problems to be Solved by the Invention] However, as shown in FIG. The structure is such that a low-resistance polysilicon layer 66 exists, and an Aj wiring layer 76 exists above the polysilicon layer 70 with a PSG film 74 interposed therebetween.

Similarly, as shown in FIG. 5, below the high-resistance polysilicon layer 78 serving as a resistive load, a low-resistance polysilicon layer 66 is provided via a silicon oxide film 68 and a silicon oxide layer 82; A low resistance polysilicon layer 80 exists with an oxide film 82 interposed therebetween, and an AJI wiring layer 76 exists above the polysilicon layer 78 with a PSG film 74 interposed therebetween.

Such a structure forms a so-called MO3 structure, and the high resistance polysilicon layer 70.80 sandwiched between the Aj wiring layer 76 and the low resistance polysilicon layer 66.80, which are the upper and lower conductive layers, are controlled by the electric potential of the upper and lower conductive layers. 78 suffers from resistance modulation and is difficult to stabilize.

In addition, in the conventional semiconductor memory device described above, as the degree of integration increases, the cell area decreases, and the parasitic capacitance held in the information storage node becomes smaller and smaller. Soft errors caused by alpha rays occur when charges induced by alpha rays reverse the potential at the information storage node, so the smaller the original charge amount of the information storage node, that is, the smaller the capacity, the more soft errors caused by alpha rays. It means that you are weak. Therefore, as the degree of integration increases, there is a problem that the device becomes more susceptible to soft errors.

Therefore, the present invention provides a semiconductor memory device that can improve the reliability of an element by stabilizing the resistance value of a resistive layer as a load against resistance modulation due to the potential of surrounding conductive layers and increasing resistance to soft errors. The object of the present invention is to provide a device and a method for manufacturing the same.

[Means for Solving the Problem] The above problem is solved by providing a conductive layer on almost the entire circumference of the resistance layer via an insulating film in a semiconductor memory device having a flip-flop type memory cell using a resistance layer as a load. This is achieved by a semiconductor memory device characterized by:

Further, in the method of manufacturing a semiconductor memory device having a flip-flop type memory cell using a resistance layer as a load, the step of removing a material film formed under the resistance layer to expose the lower surface of the resistance layer; This is achieved by a method for manufacturing a semiconductor memory device, which comprises the step of forming a conductive layer on the upper and lower surfaces of a resistive layer with an insulating film interposed therebetween.

[Function] That is, in the present invention, by covering almost the entire circumferential surface of a resistive layer forming a load with a conductive layer via an insulating film, the high-resistance layer is subjected to resistance modulation due to the potential of the conductive layers above and below it. At the same time, the capacitance of the information storage node is increased by forming a large capacitance between the resistance layer and the conductive layer covering it in the vicinity of the contact portion between the high resistance layer and the information storage node.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1(a) is a plan view of a semiconductor memory device according to an embodiment of the present invention, and FIG. 1(b) is a cross-sectional view taken along the line X--X.

A field oxide fi4 is formed on the semiconductor substrate 2 to isolate device regions. On the surface of the semiconductor substrate 2 in this element region, n+ type impurity regions 6 and 8 serving as the source and drain regions of the transfer transistor T1 and an n+ type impurity region 10 connected to the ground voltage V□ are formed.

A polysilicon layer 14 as the gate of the transfer transistor T1 is formed on the semiconductor substrate 2 sandwiched between the n+ type impurity regions 6 and 8 as the source and drain regions of the transfer transistor T3 with a gate oxide film 12 interposed therebetween. has been done.

This polysilicon layer 14 is connected to the word line WL. Similarly, a polysilicon layer 16 as the gate of the driver transistor T2 is formed on the semiconductor substrate 2 in the element region via the gate oxide film 12. The octopus polysilicon layer 16 connected to the n" type impurity region 8 serving as the drain region of the transfer transistor T3.

Furthermore, n+ type impurity region 1 connected to ground voltage Vss
0 through the silicon nitride film 18, the power supply voltage V
Polysilicon layer 20 as a power supply layer connected to CC
is formed.

Further, a non-doped polysilicon layer 22 serving as a resistive load R1 is formed on the polysilicon layer 16 via a silicon nitride film 18. This polysilicon layer 22 is
One side is connected to the polysilicon layer 16, and the other side is connected to the polysilicon layer 20 serving as a power supply layer connected to the power supply voltage ccC.

The polysilicon layer 22 serving as the resistive load R1 has its upper surface, lower surface, and side surfaces, that is, its entire circumferential surface in the vertical and horizontal directions, except for the contact portions with the polysilicon layer 16 and the polysilicon layer 20. It is covered via an oxide film 24 with a polysilicon layer 26 serving as a protective plate that is maintained at a - constant voltage.

At this time, in the vicinity of the contact portion between the polysilicon layer 22 and the polysilicon layer 16 as the resistive load R1, the non-doped polysilicon layer 22 has a low resistance due to the diffusion of impurities from the polysilicon layer 16, and this contact It has the same potential as the information storage node A in the section. Therefore, a capacitance is formed between the polysilicon layer 22 in the vicinity of the contact portion and the polysilicon layer 26 as a protective plate, and the polysilicon layer 26 as a protective plate covers the polysilicon layer 22 with the silicon oxide film 24 interposed therebetween. Since the entire circumferential surface of layer 22 contributes to the capacitive surface area,
Its capacity will be extremely large.

Furthermore, a PSG film 28 as a glabellar insulating film is formed on the entire surface, and an Ajl wiring layer 3 is connected to an n+ type impurity region 6 as a source region of a transfer transistor T3 through a contact hole opened in this PSG film 28.
0 is formed.

The A and g wiring layers 30 are connected to the bit line BL.

As described above, according to this embodiment, the high resistance polysilicon layer 22 as the resistive load R1 is the polysilicon layer 16.2.
The upper surface, lower surface and side surfaces, that is, the entire circumferential surface, except for the contact portion with 0, are covered with a polysilicon layer 26 as a protective plate kept at a constant voltage via silicon oxide 824, The resistance is not modulated by the potentials of the A1 wiring layer 30 and the low resistance polysilicon layers 16 and 20, which are conductive layers that exist above and below the high resistance polysilicon layer 22.

Further, in the vicinity of the contact portion between the non-doped polysilicon layer 22 as the resistive load R1 and the polysilicon layer 16, a polysilicon layer 26 as a protective plate covers the polysilicon layer 22 and the silicon oxide film 24 via the polysilicon layer 22 and the polysilicon layer 16. Because a very large capacitance is formed between
The capacity at the information storage node increases significantly. As a result, resistance to soft errors increases.

Next, a method for manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG.

A field oxide film 4 is selectively formed on a semiconductor substrate 2 to isolate device regions. Then, on the surface of the semiconductor substrate 2 in this element region, a gate oxide 812 with a thickness of 200 nm is formed using a thermal oxidation method. Subsequently, a contact hole 32 is opened at a predetermined location using photolithography technology (see FIG. 2(a)).

Next, after growing a polysilicon layer with a thickness of 4000 Å using the CVD (chemical vapor deposition) method, the POCj
! Phosphorus P is introduced by thermal diffusion using 3. Then, using RIE (reactive ion etching) method, CC1
, 102 atmosphere, the polysilicon layer is patterned to form polysilicon layers 14 and 16.

Furthermore, using these polysilicon layers 14, 16 and field oxide M4 as masks, arsenic ions As+ are implanted under the conditions of an acceleration voltage of 50 keV and a dose of 4X101Sam-2 to form n-ions on the surface of the semiconductor substrate 2.
A + type impurity region 6, 34° 10 is formed. At this time,
Phosphorous P impurity is also diffused from the polysilicon layer 16 through the contact hole 32, and an n+ type impurity region 36 adjacent to the n+ type impurity region 34 is formed (see FIG. 2(b)).

In this way, the n+ type impurity region 6 is used as a source region, and the n+
Transfer transistor T having type impurity regions 34 and 36 as a drain region and polysilicon layer 14 as a gate
3 is formed, and a driver transistor T2 (the n+ type impurity regions serving as the source and drain regions are not shown because they are formed perpendicular to the drawing) having the polysilicon layer 16 as a gate is formed. Ru. The n+ type impurity region 10 forms a wiring layer connected to the ground voltage s11.

The n+ type impurity regions 34 and 36 formed adjacent to each other on the surface of the semiconductor substrate 2 are regarded as an integral part and are referred to as the n+ type impurity region 8. Then, a silicon nitride film 18 having a thickness of 1000 Å is grown over the entire surface by CVD (see FIG. 2(c)).

Next, a polysilicon layer with a thickness of 4000 A was grown using the CVD method, and then arsenic ions As+ were implanted under the conditions of an acceleration voltage of 50 keV and a dose of 4 x 101 Sam-2 to lower the resistance. Then, the polysilicon layer is patterned by the RIE method in a CCl a 102 atmosphere to form a polysilicon layer 20.

This polysilicon layer 20 forms a power supply layer connected to the power supply voltage Vcc (see FIG. 2(d)).

Next, a silicon oxide film 38 having a thickness of 1000 wafers is grown by CVD. Then, by RIE method, CF
4/Silicon oxidation 11138 in H2 atmosphere
Then, the silicon nitride film 18 is selectively etched away, and contact holes 40° and 42 are opened at predetermined locations on the polysilicon layer 16 and 20, respectively (FIG. 2(e)).
reference).

Next, a film with a thickness of 10 mm is deposited on the silicon oxide WA 38 and the exposed polysilicon layer 16.
Grow 0.00 polysilicon layer. Then, the polysilicon layer is patterned in a CC14/02 atmosphere by the RIE method to form a polysilicon layer 22 (see FIG. 2(f)).

In this way, the polysilicon layer 22 provided to connect the polysilicon layer 16 and the polysilicon layer 20
has a high resistance because it is non-doped 1 with no impurities introduced therein, and forms a resistive load R1 provided between the drain region 8 of the transfer transistor T3 and the gate of the driver transistor T2 and the power supply voltage vc0.

Next, the silicon oxide film 38 is completely etched away by immersion in a hot HP solution. This also exposes the lower surface of polysilicon layer 22. Note that at this time, the silicon nitride film 18 is not etched (see FIG. 2(g)).

Next, a silicon oxide film 24 having a thickness of 200 nm is formed on the entire exposed surface of the polysilicon layer 20.22 by thermal oxidation under a reduced pressure state of approximately I TOrr. Subsequently, after growing a polysilicon layer to a thickness of 1000 on this silicon oxide film 24 and silicon nitride film 18, phosphorus P is introduced by thermal diffusion using POCjs. Then, the polysilicon layer is patterned in a CC1-/02 atmosphere using the RIE method to form a polysilicon layer 26 (see FIG. 2 (h)).
.

In this way, the polysilicon layer 26 includes the upper surface of the polysilicon layer 22 serving as the resistive load R1, excluding the contact portions with the polysilicon layer 16 and the polysilicon layer 20;
gl covering the lower surface and side surfaces, that is, the entire circumferential surface in the vertical and horizontal directions via silicon oxide M24;
form a protective plate. The polysilicon layer 26 serving as a protective plate is maintained at a constant voltage.

At this time, in the vicinity of the contact portion between the polysilicon layer 22 and the polysilicon layer 16 as the resistive load R1, the non-doped polysilicon layer 22 has the polysilicon layer 16
Impurities are diffused from the contact portion to lower the resistance, and the potential is the same as that of the information storage node A of this contact portion. Therefore,
A capacitance is formed between the polysilicon layer 22 near the contact portion and the polysilicon layer 26 serving as an IT plate. Moreover, the capacitance becomes extremely large because the entire circumferential surface of the polysilicon layer 22, which is covered by the polysilicon layer 26 serving as a protective plate via the silicon oxide film 24, contributes to the capacitance surface area.

Next, by CVD method, PS with a thickness of 0.5 μm was applied to the entire surface.
CJ928 is grown as a glabellar insulation layer.

A contact hole is then opened on n1 type impurity region 6 as a source region of transfer transistor T3. Then, an AI wiring layer 30 is formed to connect to the n+ type impurity region 6 through this contact hole (see FIG.
(See L).

In the above manufacturing method, a silicon oxide film 24 with a thickness of 200 nm is formed on the entire exposed surface of the polysilicon layer 20.22 by thermal oxidation under reduced pressure.
A silicon nitride film having a thickness of 300 nm may be grown using the D method.

[Effects of the Invention] As described above, according to the present invention, the resistance layer as a load is
Since its entire circumferential surface is covered with a conductive layer as a protective plate that is maintained at a constant voltage via an insulating film, the resistance can be modulated by the potential of the conductive layers above and below the resistance layer. I won't receive it.

In addition, in the information storage node, a very large capacitance is formed between the resistive layer and the conductive layer as a protective plate covering it via the insulating film, so the capacitance in the information storage node increases greatly. Increased resistance to soft errors.

Thereby, the reliability of the semiconductor memory device can be improved.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing a semiconductor memory device according to an embodiment of the present invention, FIG. 1(b) is a sectional view of FIG. 1(a>), and FIG. 2 is a semiconductor memory device according to an embodiment of the present invention. 3 is a circuit diagram showing a semiconductor memory device, and FIGS. 4 and 5 are sectional views each showing a conventional semiconductor memory device. In the figure, 2.52 ... Semiconductor substrate, 4.54 ... Field oxide film, 6.8,10
, 34, 36, 56, 58.60... n+ type impurity region, 12.62... gate oxide film, 14.16, 2
0,22,26,64.66゜70.72,78.80
...Borosilicon layer, 18...Silicon nitride film, 24.38,68.82...Silicon oxide film,
28.74--PSG film, 30.76--Aj wiring layer, 32.40.42--Contact ball. Figure 3 is a circuit diagram showing the cattle guiding device.

Claims (1)

[Claims] 1. A semiconductor memory device having a flip-flop type memory cell using a resistance layer as a load, characterized in that a conductive layer is provided on almost the entire circumference of the resistance layer via an insulating film. semiconductor storage device. 2. A method for manufacturing a semiconductor memory device having a flip-flop type memory cell using a resistance layer as a load, including: removing a material film formed under the resistance layer to expose the lower surface of the resistance layer; 1. A method of manufacturing a semiconductor memory device, comprising the step of forming a conductive layer on an upper surface and a lower surface of a resistive layer with an insulating film interposed therebetween.