JPH05326815A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH05326815A
JPH05326815A JP13218592A JP13218592A JPH05326815A JP H05326815 A JPH05326815 A JP H05326815A JP 13218592 A JP13218592 A JP 13218592A JP 13218592 A JP13218592 A JP 13218592A JP H05326815 A JPH05326815 A JP H05326815A
Authority
JP
Japan
Prior art keywords
die pad
semiconductor device
lead frame
cracks
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13218592A
Other languages
Japanese (ja)
Inventor
Satoshi Konishi
聡 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP13218592A priority Critical patent/JPH05326815A/en
Publication of JPH05326815A publication Critical patent/JPH05326815A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide the lead frame for a semiconductor device generating no package cracks by sudden heating in a reflow process when the semiconductor is packaged. CONSTITUTION:Notches 4 are formed on the circumference of a die pad 1 formed almost in rectangular shape. As a result, even when stress is concentrated on the circumference of the die pad 1 by the evaporative expansion of the moisture accumulated on the backside of the die pad 1, the stress can be alleviated by the abovementioned notches 4, and the generation of cracks on the package can also be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置用リードフレ
ームに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device lead frame.

【0002】[0002]

【従来の技術】図2に従来の半導体装置用リードフレー
ムを示す。図2において、半導体チップ(図示せず)を
載置するダイパッド1は矩形に形成され、その4隅がダ
イパッドサポート部2によってリードフレーム本体に支
持されている。そして、多数のインナーリード3がダイ
パッド1の周辺に配置されている。
2. Description of the Related Art FIG. 2 shows a conventional lead frame for a semiconductor device. In FIG. 2, a die pad 1 on which a semiconductor chip (not shown) is placed is formed in a rectangular shape, and its four corners are supported by the lead frame body by die pad support portions 2. A large number of inner leads 3 are arranged around the die pad 1.

【0003】半導体装置を組立てる際には、半導体チッ
プをダイパッド1の表面に接着し、半導体チップ上の電
極とインナーリード3を金属細線で接続し、その後、半
導体チップ、ダイパッド1、ダイパッドサポート部2、
インナーリード3、金属細線を覆うように樹脂で封止
し、最後に封止樹脂の外側に出たリードフレーム部分を
切断する。
When assembling a semiconductor device, a semiconductor chip is adhered to the surface of the die pad 1, the electrodes on the semiconductor chip and the inner leads 3 are connected with a thin metal wire, and then the semiconductor chip, the die pad 1, and the die pad support 2 ,
The inner lead 3 and the thin metal wire are sealed with a resin so that the lead frame portion outside the sealing resin is cut off.

【0004】[0004]

【発明が解決しようとする課題】近年、この種の半導体
装置において、特にQFPと呼ばれる表面実装型の半導
体装置においては、半導体装置をプリント基板表面に実
装する際のリフロー工程で、ダイパッド1の下方にある
樹脂にクラックが発生することが問題になっている。こ
れは、ダイパッド1の裏面に溜った水分が、リフロー工
程での急激な熱印加により気化膨張するため、ダイパッ
ド1の側面付近に応力が集中し、これが樹脂に加わっ
て、特に樹脂厚の薄いダイパッド1の下面にクラックが
発生するものと考えられる。クラックが発生することに
よって、半導体装置の耐湿性が著しく低下し、信頼性が
悪化する。
In recent years, in this type of semiconductor device, in particular, in a surface mounting type semiconductor device called QFP, a lower surface of the die pad 1 is subjected to a reflow process when the semiconductor device is mounted on the surface of a printed circuit board. There is a problem that cracks are generated in the resin. This is because the water accumulated on the back surface of the die pad 1 vaporizes and expands due to rapid heat application in the reflow process, so stress concentrates near the side surface of the die pad 1, and this stress is added to the resin, especially the die pad with a thin resin thickness. It is considered that a crack is generated on the lower surface of No. 1. Due to the occurrence of cracks, the moisture resistance of the semiconductor device is significantly reduced and the reliability is deteriorated.

【0005】本発明はこのような従来の問題を解決する
半導体装置用リードフレームを提供するものである。
The present invention provides a lead frame for a semiconductor device, which solves the above conventional problems.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置用リ
ードフレームは、ダイパッドの周縁に切り欠きを設けた
ものである。
A lead frame for a semiconductor device according to the present invention has a notch formed in the peripheral edge of a die pad.

【0007】[0007]

【作用】このようにすれば、ダイパッドの裏面に溜った
水分が、リフロー工程での急激な熱印加により気化膨張
しても、ダイパッドの周縁に設けた切り欠きによって応
力集中を防ぐことができるため、ダイパッド下方の樹脂
にクラックが発生するのを防止することができる。
By doing so, even if the water accumulated on the back surface of the die pad is vaporized and expanded by the rapid application of heat in the reflow process, stress concentration can be prevented by the notch provided in the peripheral edge of the die pad. It is possible to prevent the resin under the die pad from cracking.

【0008】[0008]

【実施例】以下、本発明の一実施例について図1ととも
に説明する。図1は、本発明を表面実装(QFP)型の
半導体装置用リードフレームに応用した実施例である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows an embodiment in which the present invention is applied to a surface mount (QFP) type semiconductor device lead frame.

【0009】図1において、半導体チップ(図示せず)
を載置するダイパッド1は全体として矩形に形成され、
その4隅がダイパッドサポート部2によってリードフレ
ーム本体に支持されている。そして、多数のインナーリ
ード3がダイパッド1の周辺に配置されている。
In FIG. 1, a semiconductor chip (not shown)
The die pad 1 on which is mounted is formed in a rectangular shape as a whole,
The four corners are supported by the lead frame body by the die pad support portion 2. A large number of inner leads 3 are arranged around the die pad 1.

【0010】さらに、この実施例においては、ダイパッ
ド1の周縁に切り欠き4を設けることにより、ダイパッ
ド1の周縁に凹凸を形成している。
Further, in this embodiment, the notch 4 is provided on the peripheral edge of the die pad 1 to form the irregularities on the peripheral edge of the die pad 1.

【0011】半導体装置を組立てる際には、半導体チッ
プをダイパッド1の表面に接着し、半導体チップ上の電
極とインナーリード3を金属細線で接続し、その後、半
導体チップ、ダイパッド1、ダイパッドサポート部2、
インナーリード3、金属細線を覆うように樹脂で封止
し、最後に封止樹脂の外側に出たリードフレーム部分を
切断する。
When assembling the semiconductor device, the semiconductor chip is adhered to the surface of the die pad 1, the electrodes on the semiconductor chip and the inner leads 3 are connected with a thin metal wire, and then the semiconductor chip, the die pad 1, and the die pad support 2 ,
The inner lead 3 and the thin metal wire are sealed with a resin so that the lead frame portion outside the sealing resin is cut off.

【0012】このようにすれば、ダイパッド1の裏面に
溜った水分が、リフロー工程での急激な熱印加により気
化膨張しても、ダイパッド1の周縁に設けた切り欠き4
によって応力集中を防ぐことができる。このため、ダイ
パッド1の下方の樹脂にクラックが発生するのを防止す
ることができる。
With this configuration, the notch 4 provided on the peripheral edge of the die pad 1 even if the water accumulated on the back surface of the die pad 1 is vaporized and expanded by the rapid heat application in the reflow process.
This can prevent stress concentration. Therefore, it is possible to prevent cracks from being generated in the resin below the die pad 1.

【0013】実験によれば、パッケージサイズが14m
m角、パッケージ厚さが1.5mm、ダイパッドサイズ
が9mm角のものを例にとると、湿度85%、温度85
℃の環境下で168時間吸湿させた場合、従来の構成で
はダイパッド1の下方の樹脂にクラックが発生したが、
本発明の実施例の構成ではクラックが発生しなかった。
Experiments have shown that the package size is 14 m.
Taking an example of an m-square, a package thickness of 1.5 mm, and a die pad size of 9 mm square, the humidity is 85% and the temperature is 85%.
When moisture was absorbed for 168 hours in an environment of ° C, cracks occurred in the resin below the die pad 1 in the conventional configuration,
No cracks were generated in the configurations of the examples of the present invention.

【0014】なお、切り欠き4の個数は、1辺当り4〜
15個の範囲内、切り欠き4の深さは0.1〜0.8mm
の範囲内で、パッケージサイズ、パッケージ厚さ、ダイ
パッドサイズ等に応じて効果が最も大きくなるものを選
択すればよい。
The number of notches 4 is 4 to 4 per side.
Within the range of 15 pieces, the depth of the notch 4 is 0.1 to 0.8 mm
Within this range, the one having the greatest effect may be selected according to the package size, the package thickness, the die pad size, and the like.

【0015】[0015]

【発明の効果】本発明の半導体装置用リードフレーム
は、ダイパッドの周縁に切り欠きを設けたものであるか
ら、ダイパッドの裏面に溜った水分が、リフロー工程で
の急激な熱印加により気化膨張しても、ダイパッドの周
縁に設けた切り欠きによって応力集中を防ぐことができ
る。このため、ダイパッド下方の樹脂にクラックが発生
するのを防止することができ、半導体装置の信頼性を飛
躍的に高めることができる。
Since the lead frame for a semiconductor device of the present invention is provided with a notch at the periphery of the die pad, the water accumulated on the back surface of the die pad is vaporized and expanded by the rapid application of heat in the reflow process. However, stress concentration can be prevented by the notch provided in the peripheral edge of the die pad. Therefore, it is possible to prevent the resin under the die pad from being cracked, and it is possible to dramatically improve the reliability of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における半導体装置用リード
フレームの要部平面図
FIG. 1 is a plan view of a main part of a lead frame for a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置用リードフレームの要部平面
FIG. 2 is a plan view of a main part of a conventional lead frame for a semiconductor device.

【符号の説明】[Explanation of symbols]

1 ダイパッド 2 ダイパッドサポート部 3 インナーリード 4 切り欠き 1 Die pad 2 Die pad support part 3 Inner lead 4 Notch

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体チップを載置するダイパッドの周縁
に切り欠きを設けたことを特徴とする半導体装置用リー
ドフレーム。
1. A lead frame for a semiconductor device, wherein a notch is provided in a peripheral edge of a die pad on which a semiconductor chip is mounted.
JP13218592A 1992-05-25 1992-05-25 Lead frame for semiconductor device Pending JPH05326815A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13218592A JPH05326815A (en) 1992-05-25 1992-05-25 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13218592A JPH05326815A (en) 1992-05-25 1992-05-25 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH05326815A true JPH05326815A (en) 1993-12-10

Family

ID=15075382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13218592A Pending JPH05326815A (en) 1992-05-25 1992-05-25 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH05326815A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468993A (en) * 1992-02-14 1995-11-21 Rohm Co., Ltd. Semiconductor device with polygonal shaped die pad
US5945731A (en) * 1995-10-11 1999-08-31 Nec Corporation Resin encapsulated semiconductor device and method for manufacturing the same
US7964942B2 (en) 2003-05-28 2011-06-21 Yamaha Corporation Lead frame having a die stage smaller than a semiconductor device and a semiconductor device using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468993A (en) * 1992-02-14 1995-11-21 Rohm Co., Ltd. Semiconductor device with polygonal shaped die pad
US5945731A (en) * 1995-10-11 1999-08-31 Nec Corporation Resin encapsulated semiconductor device and method for manufacturing the same
US7964942B2 (en) 2003-05-28 2011-06-21 Yamaha Corporation Lead frame having a die stage smaller than a semiconductor device and a semiconductor device using the same

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