JPH04127459A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04127459A
JPH04127459A JP24825990A JP24825990A JPH04127459A JP H04127459 A JPH04127459 A JP H04127459A JP 24825990 A JP24825990 A JP 24825990A JP 24825990 A JP24825990 A JP 24825990A JP H04127459 A JPH04127459 A JP H04127459A
Authority
JP
Japan
Prior art keywords
island
frame
resin layer
leads
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24825990A
Other languages
Japanese (ja)
Inventor
Hiroyuki Nakayama
中山 浩幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP24825990A priority Critical patent/JPH04127459A/en
Publication of JPH04127459A publication Critical patent/JPH04127459A/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the bend of outer leads even in a characteristic checking process by forming a resin layer for supporting the outer leads. CONSTITUTION:A package 7 is formed by sealing an island and semiconductor chip 3 with a resin after the chip 3 is mounted on the island of a lead frame which is coupled by means of the first tiebar 4A near the island and second tiebar 4B far from the island and connected to a frame 1. At the time of forming the package, a resin layer 2 is also formed between the first tiebar 4A and package 7. Then a resin layer 5 for supporting outer leads is formed in the area surrounded by the second tiebar 4B, outer leads 6, and frame 1. Since the outer leads 6 are connected with each other by means of the resin layer 5 after the leads 6 are separated from the frame and first and second tiebars 4A and 4B, the leads seldom bend even when a load is applied to the leads 6 at checking time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に樹脂封止型
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

一般に樹脂封止型半導体装置の製造工程では、図2(a
)に示すように、周囲にタイバー4により連絡された外
部リード6を有するリードフレームのアイランドに半導
体チップ3を搭載したのち、この半導体チップ3を樹脂
封止してパッケージ7を形成していた。この時樹脂層は
、外部り−ド6とタイバー4との間とに形成されていた
。この後、特性チエツクの必要性から、図2(b)に示
すように、外部リード6とフレーム1とが切り離されて
いた。
Generally, in the manufacturing process of resin-sealed semiconductor devices,
), a semiconductor chip 3 was mounted on an island of a lead frame having external leads 6 connected by tie bars 4 around the island, and then the semiconductor chip 3 was sealed with resin to form a package 7. At this time, the resin layer was formed between the outer cord 6 and the tie bar 4. After this, due to the necessity of checking the characteristics, the external lead 6 and the frame 1 were separated as shown in FIG. 2(b).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上述した半導体装置の製造工程において
は、外部リード切断後、特性をチエツクする工程におい
て、外部リードが支持されていない状態で、コンタクト
ビン等により外部から外部リードに負荷がかかるため、
外部リード6が曲がるという欠点を持っていた。本発明
の目的は、上記欠点を除去し、負荷によっても外部リー
ドが曲がることのない半導体装置の製造方法を提供する
ことにある。
However, in the manufacturing process of the semiconductor device described above, in the step of checking the characteristics after cutting the external leads, a load is applied to the external leads from the outside by a contact bottle or the like without being supported.
It had the disadvantage that the external lead 6 was bent. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above drawbacks and prevents external leads from bending even under load.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、アイランドに近い第
1のタイバーとアイランドから離れた第2のタイバーに
より連絡され、かつフレームに接続された外部リードと
を有するリードフレームのアイランドに半導体チップを
搭載する工程と、このアイランド及び半導体チップを樹
脂封止しパッケージを形成後前記第2のタイバーと外部
リードとフレームとに囲まれた部分に外部リード支持用
の樹脂層を形成する工程とを含んで精成される。
A method for manufacturing a semiconductor device of the present invention includes mounting a semiconductor chip on an island of a lead frame that has an external lead connected to the frame and connected by a first tie bar close to the island and a second tie bar remote from the island. and a step of forming a resin layer for supporting external leads in a portion surrounded by the second tie bar, external leads, and frame after forming a package by sealing the island and the semiconductor chip with resin. Be refined.

〔実施例〕〔Example〕

以下本発明の実施例について図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.

図1(a)〜(c)は本発明の一実施例を説明するなめ
のリードフレーム及びパッケージの上面図である。
FIGS. 1(a) to 1(c) are top views of a lead frame and a package illustrating an embodiment of the present invention.

抜ず図1(a)に示すように、アイランド(図示せず)
に近い第1のタイバー4Aとアイランドから離れた第2
のタイバー4Bにより連結され、かつフレーム1に接続
されたリードフレームのアイランドに半導体チップ3を
搭載したのち、このアイランド及び半導体チップ3を樹
脂で封止してパッケージ7を形成する。この時、第1の
タイバー4Aとパッケージ7の間にも樹脂層2が形成さ
れる。次で、第2のタイバー4Bと外部リード6とフレ
ーム1とで囲まれた部分に外部リード支持用樹脂層5を
形成する。
As shown in Figure 1(a), an island (not shown)
The first tie bar 4A is close to the island and the second tie bar is far from the island.
A semiconductor chip 3 is mounted on an island of a lead frame connected by tie bars 4B and connected to the frame 1, and then the island and the semiconductor chip 3 are sealed with resin to form a package 7. At this time, the resin layer 2 is also formed between the first tie bar 4A and the package 7. Next, an external lead supporting resin layer 5 is formed in a portion surrounded by the second tie bar 4B, the external lead 6, and the frame 1.

次に、図1(b)に示すように、樹脂層2、第1のタイ
バー4A及び第2のタイバー4Bを既知の切断方法によ
り除去する。
Next, as shown in FIG. 1(b), the resin layer 2, the first tie bar 4A, and the second tie bar 4B are removed by a known cutting method.

次に図1(C)に示すように、外部リード支持用樹脂層
5を、外部リード6の間に残した状態で切断する。
Next, as shown in FIG. 1C, the external lead supporting resin layer 5 is cut while remaining between the external leads 6.

このように本実施例によれば、外部リード6をフレーム
1や第1及び第2のタイバー4A、4Bから切り離した
後でも、外部リード6は外部リード支持用樹脂層5によ
り相互に接続されているため、チエツク時に負荷が与え
られても曲ることはほとんどなくなる。
According to this embodiment, even after the external leads 6 are separated from the frame 1 and the first and second tie bars 4A and 4B, the external leads 6 are still connected to each other by the external lead supporting resin layer 5. Because of this, there is almost no bending even if a load is applied during a check.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、外部リードを支持するた
めの樹脂層を形成することにより、特性チエツク工程に
おいても外部リードの曲がりの少ない半導体装置が得ら
れるという効果がある。
As explained above, the present invention has the advantage that by forming a resin layer for supporting the external leads, a semiconductor device with less bending of the external leads can be obtained even in the characteristic checking process.

【図面の簡単な説明】[Brief explanation of the drawing]

図1(a)〜(c)は本発明の一実施例を説明するため
のリードフレーム及びパッケージの上面図、図2(a>
、(b)は従来例を説明するためのリードフレーム及び
パッケージの上面図である。 1・・・フレーム、2・・・樹脂層、3・・・半導体チ
ップ、4・・・タイバー 4A・・・第1のタイバー 
4B・・・第2のタイバー、5・・・外部リード支持用
樹脂層、6・・・外部リード、7・・・パッケージ。
1(a) to (c) are top views of a lead frame and a package for explaining one embodiment of the present invention, and FIG. 2(a>
, (b) are top views of a lead frame and a package for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Frame, 2... Resin layer, 3... Semiconductor chip, 4... Tie bar 4A... First tie bar
4B... Second tie bar, 5... Resin layer for supporting external leads, 6... External leads, 7... Package.

Claims (1)

【特許請求の範囲】[Claims]  アイランドに近い第1のタイバーとアイランドから離
れた第2のタイバーにより連絡され、かつフレームに接
続された外部リードとを有するリードフレームのアイラ
ンドに半導体チップを搭載する工程と、このアイランド
及び半導体チップを樹脂封止しパッケージを形成後前記
第2のタイバーと外部リードとフレームとに囲まれた部
分に外部リード支持用の樹脂層を形成する工程とを含む
ことを特徴とする半導体装置の製造方法。
A step of mounting a semiconductor chip on an island of a lead frame having an external lead connected to the frame by a first tie bar close to the island and a second tie bar remote from the island, and mounting the island and the semiconductor chip. A method of manufacturing a semiconductor device, comprising the step of forming a resin layer for supporting external leads in a portion surrounded by the second tie bar, external leads, and frame after forming a package by resin sealing.
JP24825990A 1990-09-18 1990-09-18 Manufacture of semiconductor device Pending JPH04127459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24825990A JPH04127459A (en) 1990-09-18 1990-09-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24825990A JPH04127459A (en) 1990-09-18 1990-09-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04127459A true JPH04127459A (en) 1992-04-28

Family

ID=17175491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24825990A Pending JPH04127459A (en) 1990-09-18 1990-09-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04127459A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5381073A (en) * 1976-12-27 1978-07-18 Hitachi Ltd Oroduction of resin seal type semiconductor device and lead frame used the same
JPS61144852A (en) * 1984-12-19 1986-07-02 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5381073A (en) * 1976-12-27 1978-07-18 Hitachi Ltd Oroduction of resin seal type semiconductor device and lead frame used the same
JPS61144852A (en) * 1984-12-19 1986-07-02 Hitachi Ltd Semiconductor device

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