JPH03280566A - Surface mounting type semiconductor device - Google Patents
Surface mounting type semiconductor deviceInfo
- Publication number
- JPH03280566A JPH03280566A JP8275190A JP8275190A JPH03280566A JP H03280566 A JPH03280566 A JP H03280566A JP 8275190 A JP8275190 A JP 8275190A JP 8275190 A JP8275190 A JP 8275190A JP H03280566 A JPH03280566 A JP H03280566A
- Authority
- JP
- Japan
- Prior art keywords
- sealing member
- lead terminals
- lower sealing
- outer lead
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000007789 sealing Methods 0.000 claims abstract description 28
- 238000005452 bending Methods 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野J
本発明は表面実装型半導体装置に関し、特に外部リード
端子の引出し形状に関する。
【従来の技術l
第4図(al 、 (b)および第5図(a) 、 l
b)はそれぞれ従来の異なる2つの表面実装型半導体装
置の平面図および側面図を示すもので、通常、外部リー
ド端子2は先端部を下部封着部材1bの外側または内側
に向は折り曲げ成形されて引出される。ここで、1aは
下部封着部材1bと協同して半導体チップ(図示しない
)を気密封止する上部封着部材である。
【発明が解決しようとする課題1
しかしながら、これら従来の表面実装型半導体装置は、
下部封着部材】bの側面が配線基板に対していずれも垂
直となる形状に成形されているので、第4図(at 、
(blのように外部リード端子2が外向きに折り曲げ
成形される場合は兎も角、高密度実装に適する第5図(
a) 、 (b)の如き内向き成形の場合には、下部封
着部材1bの角縁が邪魔になって、外部リード端子2の
引出し形状番こ不揃いが生じ易い不都合さがある。特に
最近ではこれらの半導体装置は自動実装されることが多
いので、外部リード端子の引出し形状の不揃いは半田付
不良の発生頻度を助長し好ましくない。
本発明の目的は、上記の情況に鑑み、外部す−ド端子の
折り曲げ成形の際、引出し形状に不揃いが生じ易い従来
封着部材の構造的欠陥を改善した表面実装型半導体装置
を提供することである。
1課題を解決するための手段1
本発明によれば1表面実装型半導体装置は。
半導体チップと、前2半導体チップを気密封止する上部
および下部の対部材からなる封着部材と、前記封着部材
の下部封着部材の側面から裏面にかけて形成される緩や
かな曲率または角度の傾斜面と、前記傾斜面に沿って先
端部を内向きに引出し成形される前記半導体チップの外
部リード端子とを含んで構成される。
【 作 用 1
本発明によれば、外部リード端子は、下部封着部材の側
面から裏面にかけて形成された傾斜面を案内として内向
きに折り曲げ成形されるので、従来生じ易かった外部リ
ード端子の引出し形状の不揃いは解決される。
【実施例1
次に本発明について図面を参照して詳細に説明する。
第1図 181および(b) 、 (clはそれぞれ本
発明の一実施例を示す表面実装型半導体装置の平面図お
よび側面図である0本実施例によれば、3端子の半導体
チップ(図示しない)は、上部封着部材1aおよび下部
封着部材1bの対部材からなる封着部材により気密封止
され、3つの外部リード端子2は下部封着部材1bの側
面から裏面にかけて形成された緩やかな角度の傾斜面3
を案内として先端部がそれぞれ折り曲げ成形される。
第2図(a1〜(clは本発明表面実装型半導体装置の
外部リード端子の折り曲げ成形工程図で、外部リード端
子2の先端部が下部封着部材lbの傾斜面3を案内とす
る2回目の折り曲げ工程で、引出し形状にバラツキを生
じることなく成形されることを示す。
第3図 1alおよび(blはそれぞれ本発明の他の実
施例を示す表面実装型半導体装置の平面図および側面図
で、半導体チップ(図示しない)が2端子の場合を示し
たものである0本実施例においても、2つの外部リード
端子2の先端部は下部封着部材1bの傾斜面3を案内と
してそれぞれ折り曲げ成形されて引出される。
以上は傾斜面3が緩やかな角度で直線的に形成された場
合を説明したが、緩やかな曲率の円弧面で形成されても
よい。
【発明の効果1
以上詳細に説明したように、本発明によれば、外部リー
ド端子の先端部が配線基板に対してそれぞれ同一角度を
保つ形状に成形された表面実装型半導体装置が得られる
ので、自動実装される際の半田付不良障害を著しく低減
できる効果がある。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J] The present invention relates to a surface-mounted semiconductor device, and more particularly to the shape of an external lead terminal. [Prior art l Fig. 4 (al, (b)) and Fig. 5 (a), l
b) shows a plan view and a side view of two different conventional surface mount semiconductor devices, respectively. Usually, the external lead terminal 2 is formed by bending the tip end toward the outside or inside of the lower sealing member 1b. It is pulled out. Here, 1a is an upper sealing member that hermetically seals a semiconductor chip (not shown) in cooperation with lower sealing member 1b. [Problem to be solved by the invention 1] However, these conventional surface-mounted semiconductor devices
Lower sealing member] Since the side surfaces of b are formed in a shape perpendicular to the wiring board,
(If the external lead terminals 2 are bent outward as shown in bl, this is a problem, as shown in Figure 5, which is suitable for high-density mounting.)
In the case of inward molding as in a) and (b), there is a problem that the corner edges of the lower sealing member 1b get in the way and the external lead terminals 2 are likely to have irregularities in the drawer shape and size. In particular, these semiconductor devices are often automatically mounted these days, so irregularities in the shape of external lead terminals are undesirable because they increase the frequency of soldering defects. In view of the above circumstances, an object of the present invention is to provide a surface mount type semiconductor device that improves the structural defects of conventional sealing members, which tend to cause irregularities in the drawer shape when bending and forming external board terminals. It is. 1 Means for Solving the Problems 1 According to the present invention, a surface mount type semiconductor device is provided. A semiconductor chip, a sealing member consisting of a pair of upper and lower members for hermetically sealing the first two semiconductor chips, and a gentle curvature or angular inclination formed from the side surface to the back surface of the lower sealing member of the sealing member. and an external lead terminal of the semiconductor chip, which is molded by drawing the tip end inward along the inclined surface. [Function 1] According to the present invention, the external lead terminal is bent inward using the slope formed from the side surface to the back surface of the lower sealing member as a guide, so that the external lead terminal can be easily pulled out Shape irregularities are resolved. Example 1 Next, the present invention will be described in detail with reference to the drawings. 181 and (b), (cl are respectively a plan view and a side view of a surface-mounted semiconductor device showing one embodiment of the present invention. According to this embodiment, a three-terminal semiconductor chip (not shown) is used. ) is hermetically sealed by a sealing member consisting of a pair of upper sealing member 1a and lower sealing member 1b, and the three external lead terminals 2 are connected to a gentle groove formed from the side surface to the back surface of lower sealing member 1b. Angular slope 3
The tips are bent and formed using the guide as a guide. FIG. 2 (a1 to (cl) are diagrams of the bending and forming process of the external lead terminal of the surface-mounted semiconductor device of the present invention, in which the tip of the external lead terminal 2 is guided by the inclined surface 3 of the lower sealing member lb. Figure 3 1al and (bl are respectively a plan view and a side view of a surface-mounted semiconductor device showing other embodiments of the present invention. In this embodiment, the tips of the two external lead terminals 2 are bent and formed using the inclined surface 3 of the lower sealing member 1b as a guide. The case where the inclined surface 3 is formed linearly at a gentle angle has been described above, but it may also be formed as a circular arc surface with a gentle curvature. [Effect of the invention 1] Detailed explanation above. As described above, according to the present invention, it is possible to obtain a surface mount type semiconductor device in which the tips of the external lead terminals are formed in a shape that maintains the same angle with respect to the wiring board, so that soldering during automatic mounting can be achieved. This has the effect of significantly reducing defects and failures.
第1図 (a)および(b) 、 (clはそれぞれ本
発明の一実施例を示す表面実装型半導体装置の平面図お
よび側面図、第2図 (a)〜(c)は本発明表面実装
型半導体装置の外部リード端子の折り曲げ成形工程図、
第3図(atおよび(blはそれぞれ本発明の他の実施
例を示す表面実装型半導体装置の平面図および側面図、
第4図(a) 、 lb)および第5図(at 、 (
blはそれぞれ従来の異なる2つの表面実装型半導体装
置の平面図および側面図である。
1a・・・上部封着部材、
1b・・・下部封着部材、
2・・・外部リード端子、
3・・・傾斜面。
特
許
出
願
人
日
本
電
気
株
式
区
へ
味Figures 1 (a) and (b), (cl are respectively a plan view and a side view of a surface mount type semiconductor device showing one embodiment of the present invention, and Figures 2 (a) to (c) are surface mount semiconductor devices according to the present invention. Bending and forming process diagram for external lead terminals of type semiconductor devices,
FIG. 3 (at and (bl are respectively a plan view and a side view of a surface-mounted semiconductor device showing another embodiment of the present invention,
Figure 4 (a), lb) and Figure 5 (at, (
bl is a plan view and a side view of two different conventional surface mount semiconductor devices, respectively. 1a... Upper sealing member, 1b... Lower sealing member, 2... External lead terminal, 3... Inclined surface. Patent applicant NEC Co., Ltd.
Claims (1)
部および下部の対部材からなる封着部材と、前記封着部
材の下部封着部材の側面から裏面にかけて形成される緩
やかな曲率または角度の傾斜面と、前記傾斜面に沿って
先端部を内向きに引出し成形される前記半導体チップの
外部リード端子とを含むことを特徴とする表面実装型半
導体装置。A sealing member consisting of a semiconductor chip, a pair of upper and lower members for hermetically sealing the semiconductor chip, and a sloped surface with a gentle curvature or angle formed from a side surface to a back surface of the lower sealing member of the sealing member. and an external lead terminal of the semiconductor chip, which is molded by drawing out a tip end inward along the inclined surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8275190A JPH03280566A (en) | 1990-03-29 | 1990-03-29 | Surface mounting type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8275190A JPH03280566A (en) | 1990-03-29 | 1990-03-29 | Surface mounting type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03280566A true JPH03280566A (en) | 1991-12-11 |
Family
ID=13783141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8275190A Pending JPH03280566A (en) | 1990-03-29 | 1990-03-29 | Surface mounting type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03280566A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0843326A2 (en) * | 1996-11-19 | 1998-05-20 | Nec Corporation | Chip type electronic part |
US6433418B1 (en) | 1998-07-24 | 2002-08-13 | Fujitsu Limited | Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism |
-
1990
- 1990-03-29 JP JP8275190A patent/JPH03280566A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0843326A2 (en) * | 1996-11-19 | 1998-05-20 | Nec Corporation | Chip type electronic part |
EP0843326A3 (en) * | 1996-11-19 | 1999-08-25 | Nec Corporation | Chip type electronic part |
US6433418B1 (en) | 1998-07-24 | 2002-08-13 | Fujitsu Limited | Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism |
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