JPS58180040A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent disconnection at the step parts of contact holes, while to contrive to enhance yield of the titled device by a method wherein an interlayer insulating film 9 to insulate between a first metal mutual wiring positioning at the lower layer and a second metal mutual wiring positioning at the upper layer is left only at the part of the first metal mutual wiring. CONSTITUTION:The second interlayer insulating film 9 to insulate between the first metal mutual wiring 8 and the second metal mutual wiring 10 covers up to the prescribed interval R1 from both the edges of the first metal mutual wiring 8 as to contain the first metal mutual wiring 8, and the interlayer insulating film 9 at the parts outside from the intervals R1 is removed. According to construction like this, the difference in level of contact holes C2 to connect between polycrystalline silicon films 6 or an impurity semiconductor layer 4 and the second metal mutual wiring 10 becomes only to the amount of film thickness of a first interlayer insulating film 7 between the polycrystalline silicon films 5, 6 or the impurity semiconductor layers 3, 4 and the first metal mutual wiring 8. Accordingly the difference in level of the contact holes C2 is mitigated as compared with the usual structure, and fear of disconnection of the second metal mutual wiring 10 is reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having multilayer metal interconnections.

In recent years, with advances in microfabrication technology, semiconductor integrated circuit devices have become more dense and highly integrated, and the performance of the devices has been significantly improved. Along with this, research and development have been actively conducted to increase the number of layers of metal interconnections in devices, but conventional multilayer metal interconnection techniques have had the following problems.

That is, in a two-layer metal interconnection structure as shown in FIG.
When connecting the metal interconnect 10 located in the upper layer to the contact hole 7 formed in the first interlayer insulating film 7 and the second interlayer insulating film 9, At this time, if the film chambers of the first interlayer insulation 111 film 7 and the second interlayer insulation @9 were different, the shape of the contact hole became an overhang in the process of forming the contact hole (C). ,
Also, since the film thickness between each layer is thick, contact (NCs)
The difference in level between the contact holes (CI) becomes steep, and the second metal interconnection lines are difficult to connect at the step of the contact hole (CI), resulting in lower yields and lower quality of the device. In addition, l is a semiconductor substrate,
2 is a field oxide film;

The contact hole (CI) penetrates only the 10th interlayer insulating film 7 and is connected to the impurity semiconductor layer 3 or the polycrystalline silicon film 6, and the contact hole (Cs) passes through the second interlayer insulating film 9.
Penetrating only.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above drawbacks and provide a high-density semiconductor integrated circuit device with excellent quality. In a semiconductor integrated circuit device having a multilayer metal interconnection formed in a semiconductor integrated circuit device, a non-insulating insulating film for insulating and separating a first metal interconnection and a second metal interconnection located in different layers from each other is provided. It is formed so as to include the first metal interconnection part, and in the part where the second metal interconnection is not formed, the layer barrier separation pattern is removed and the second metal interconnection part is removed. An embodiment of a semiconductor integrated circuit device according to the present invention will be described with reference to the drawings. . FIG. 2 is a cross-sectional view of a two-layer metal interconnection structure according to the present invention; the same functions as in FIG. 1 are designated by the same reference numerals.

In the figure, a first metal interconnect 8 and a second metal interconnect lO
A rounded second interlayer insulating film 9 that insulates the first metal interconnection 8B covers the first metal interconnection 8B from both ends to a predetermined distance R1, and covers the first metal interconnection 8B from both ends to a predetermined distance R1. In the outer portion, the interlayer insulating film 9 is removed. According to this structure, polycrystalline silicon film 6. Alternatively, a contact hole for connecting the impurity semiconductor layer 4 and the second metal interconnection lO (the step of C is formed between the polycrystalline silicon films 5 and 6 or the impurity semiconductor layers 3 and 4 and the first metal interconnection 80). It is only the thickness of the first interlayer insulating film 7 between them.Therefore, as shown in Figure 1.K Mori 1.57
□To hole (c8). The step height is significantly reduced and the second metal interconnect i.

The risk of wire breakage is reduced as you wear it. In FIG. 2, if the distance 3 from both ends of the second interlayer insulating film 9 to the end of the contact hole (Cm) is too small, the contact hole (CI)
The above-mentioned interval 3 is set so as not to interfere with the coverage of the second metal interconnection 10 at the contact hole (C force).

In the embodiments according to the present invention, the case of two-layer metal interconnection has been described, but it goes without saying that the present invention can also be applied to a multilayer structure.

As described in detail above, according to the present invention, in a two-layer metal interconnect structure, an interlayer that insulates the first metal interconnect #8 located in the lower layer and the second metal interconnect #8 located in the upper layer The insulating film 9 remains only on the first metal interconnection 8 and has been removed on other parts. Therefore, the second metal interconnection 10 and the polycrystalline silicon film 6
Alternatively, the level difference in the contact hole (Cm) for connecting the impurity semiconductor layer 4 is moderately reduced, and the second metal interconnect 10 is no longer disconnected at the level difference in the contact hole (Cm), which improves the yield of the device. The decline can be prevented.

Further, according to the present invention, in the past, the first metal interconnection Is
8 and the second interlayer insulating film 9 between the second metal interconnect lO
When plasma vapor phase grown silicon nitride was used as a plasma vapor phase grown silicon nitride, the damage caused by the stress of the plasma vapor grown silicon nitride affected the electrical characteristics of the device, causing characteristic deterioration, but the structure of the present invention By doing so, the above-mentioned stress can be dispersed, damage can be reduced, and deterioration of electrical characteristics can be prevented. As mentioned above, the present invention is an excellent high quality product with a good yield. A high-performance, high-density semiconductor integrated circuit device can be realized, and the effects thereof are very large.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional two-layer metal interconnect structure, and FIG. 2 is a cross-sectional view of a structure according to the present invention. In the figure, %l...semiconductor substrate%2...
...Field oxide film% 3.4...Impurity semiconductor layer, 5゜6...Polycrystalline silicon model, 7
...First interlayer insulating film, 8...First metal interconnection, 9...Second interlayer insulating film, lO...
...Second metal interconnection% C1s C1@C@...
...This is a contact hole. ) Procedural amendment (Own ship 5E3.2.28 Showa year 1984 1983 1983 Patent Office Commissioner 1, Indication of the case 1982 Patent Application No. 631)
No. 46 No. 2, Title of the invention: Semiconductor integrated circuit device 3, Relationship with the person making the amendment: Applicant: 5-33-1-4, Shiba, Minato-ku, Tokyo, Agent 5, 11: Claim for patent in the description Scope column 6, Contents of amendment (1) The statement of the scope of claims in the specification will be corrected as shown in the attached sheet. 7. Attachment: 1 copy amended His patent claims ``In a semiconductor integrated circuit device having predetermined circuit elements and having multilayer metal interconnections formed on the whole surface of a living and dead conductor substrate, the semiconductor integrated circuit devices are located in different layers from each other. Layer separation I for insulating and separating the first metal interconnect and the second metal interconnect
an I& group is formed over and including the second metal interconnect portion, and the second metal interconnect portion is formed over the first metal interconnect portion;
1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is formed on a second metal interconnection via the interlayer insulating film, and is formed on a portion where the second metal interconnection is not formed. J

Claims (1)

[Claims] In a semiconductor integrated circuit device having multilayer metal interconnections formed on the entire surface of a semiconductor substrate on which predetermined circuit elements are mounted, first metal interconnections and second metal interconnections located in different layers are insulated. An interlayer insulating film for isolation is formed to cover and include the second metal interconnection portion, and a core interlayer insulating film is formed in the portion where the first metal interconnection portion is not formed. A semiconductor integrated circuit device characterized in that the second metal interconnection is formed on the first metal interconnection via the interlayer insulating film.