JPS58177032A - レベル変換回路 - Google Patents

レベル変換回路

Info

Publication number
JPS58177032A
JPS58177032A JP57058807A JP5880782A JPS58177032A JP S58177032 A JPS58177032 A JP S58177032A JP 57058807 A JP57058807 A JP 57058807A JP 5880782 A JP5880782 A JP 5880782A JP S58177032 A JPS58177032 A JP S58177032A
Authority
JP
Japan
Prior art keywords
transistor
voltage
level
base
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57058807A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0427732B2 (enrdf_load_stackoverflow
Inventor
Toshihiko Matsumura
俊彦 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57058807A priority Critical patent/JPS58177032A/ja
Publication of JPS58177032A publication Critical patent/JPS58177032A/ja
Publication of JPH0427732B2 publication Critical patent/JPH0427732B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
JP57058807A 1982-04-08 1982-04-08 レベル変換回路 Granted JPS58177032A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57058807A JPS58177032A (ja) 1982-04-08 1982-04-08 レベル変換回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57058807A JPS58177032A (ja) 1982-04-08 1982-04-08 レベル変換回路

Publications (2)

Publication Number Publication Date
JPS58177032A true JPS58177032A (ja) 1983-10-17
JPH0427732B2 JPH0427732B2 (enrdf_load_stackoverflow) 1992-05-12

Family

ID=13094866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57058807A Granted JPS58177032A (ja) 1982-04-08 1982-04-08 レベル変換回路

Country Status (1)

Country Link
JP (1) JPS58177032A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193836U (enrdf_load_stackoverflow) * 1987-12-14 1989-06-20

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531345A (en) * 1978-08-28 1980-03-05 Fujitsu Ltd Level conversion circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531345A (en) * 1978-08-28 1980-03-05 Fujitsu Ltd Level conversion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193836U (enrdf_load_stackoverflow) * 1987-12-14 1989-06-20

Also Published As

Publication number Publication date
JPH0427732B2 (enrdf_load_stackoverflow) 1992-05-12

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