JPS58158951A - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法

Info

Publication number
JPS58158951A
JPS58158951A JP57042460A JP4246082A JPS58158951A JP S58158951 A JPS58158951 A JP S58158951A JP 57042460 A JP57042460 A JP 57042460A JP 4246082 A JP4246082 A JP 4246082A JP S58158951 A JPS58158951 A JP S58158951A
Authority
JP
Japan
Prior art keywords
plating
metallized layer
layer
metallized
die stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57042460A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0414503B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Tetsushi Wakabayashi
哲史 若林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57042460A priority Critical patent/JPS58158951A/ja
Publication of JPS58158951A publication Critical patent/JPS58158951A/ja
Publication of JPH0414503B2 publication Critical patent/JPH0414503B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP57042460A 1982-03-16 1982-03-16 半導体パッケージの製造方法 Granted JPS58158951A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57042460A JPS58158951A (ja) 1982-03-16 1982-03-16 半導体パッケージの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57042460A JPS58158951A (ja) 1982-03-16 1982-03-16 半導体パッケージの製造方法

Publications (2)

Publication Number Publication Date
JPS58158951A true JPS58158951A (ja) 1983-09-21
JPH0414503B2 JPH0414503B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-03-13

Family

ID=12636678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57042460A Granted JPS58158951A (ja) 1982-03-16 1982-03-16 半導体パッケージの製造方法

Country Status (1)

Country Link
JP (1) JPS58158951A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268044A (ja) * 1988-04-19 1989-10-25 Shinko Electric Ind Co Ltd セラミックパッケージおよびその製造方法
JPH02142149A (ja) * 1988-11-22 1990-05-31 Minolta Camera Co Ltd プリント基板の製造方法
US5206188A (en) * 1990-01-31 1993-04-27 Ibiden Co., Ltd. Method of manufacturing a high lead count circuit board
JP2015230902A (ja) * 2014-06-03 2015-12-21 日本特殊陶業株式会社 配線基板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268044A (ja) * 1988-04-19 1989-10-25 Shinko Electric Ind Co Ltd セラミックパッケージおよびその製造方法
JPH02142149A (ja) * 1988-11-22 1990-05-31 Minolta Camera Co Ltd プリント基板の製造方法
US5206188A (en) * 1990-01-31 1993-04-27 Ibiden Co., Ltd. Method of manufacturing a high lead count circuit board
JP2015230902A (ja) * 2014-06-03 2015-12-21 日本特殊陶業株式会社 配線基板

Also Published As

Publication number Publication date
JPH0414503B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-03-13

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