JPS5796546A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5796546A
JPS5796546A JP17355780A JP17355780A JPS5796546A JP S5796546 A JPS5796546 A JP S5796546A JP 17355780 A JP17355780 A JP 17355780A JP 17355780 A JP17355780 A JP 17355780A JP S5796546 A JPS5796546 A JP S5796546A
Authority
JP
Japan
Prior art keywords
film
wiring
layer
mosi2
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17355780A
Other languages
Japanese (ja)
Other versions
JPS6146057B2 (en
Inventor
Toru Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17355780A priority Critical patent/JPS5796546A/en
Publication of JPS5796546A publication Critical patent/JPS5796546A/en
Publication of JPS6146057B2 publication Critical patent/JPS6146057B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide a high speed performance and a multi-layer wiring by a method wherein a wiring of silicate with a high melting point is formed on a high density impurity layer positioned at the level lower than the main surface of a substrate and at the same time a wiring portion and a semiconductor region are seperated by an oxide film of the silicate with a high melting point. CONSTITUTION:After an SiO2 film 2 and an Si3N4 film 3 are formed on a P tyep Si substrate an Mo film is formed. As ion is implanted into a specified portion and is made react on the substrate by a thermal processing to form an MoSi2 film and at the same time on n<+> layer 8 is formed. Then an Si3N4 pattern is formed on the MoSi2 film and an oxide film 10 of the MoSi2 is formed by a thermal oxidization, so that a wiring layer 11 is formed and at the same time the wiring portion and the element portion are seperated to each other. With the above configuration, a high speed perfomance, a multi-layer wiring which has high reliabity and a miniaturization of the element can be achieved.
JP17355780A 1980-12-09 1980-12-09 Semiconductor device Granted JPS5796546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17355780A JPS5796546A (en) 1980-12-09 1980-12-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17355780A JPS5796546A (en) 1980-12-09 1980-12-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5796546A true JPS5796546A (en) 1982-06-15
JPS6146057B2 JPS6146057B2 (en) 1986-10-11

Family

ID=15962747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17355780A Granted JPS5796546A (en) 1980-12-09 1980-12-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5796546A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0641174U (en) * 1992-10-30 1994-05-31 ミツミ電機株式会社 Soldering equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413283A (en) * 1977-06-30 1979-01-31 Ibm Method of forming metal silicide layer on substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413283A (en) * 1977-06-30 1979-01-31 Ibm Method of forming metal silicide layer on substrate

Also Published As

Publication number Publication date
JPS6146057B2 (en) 1986-10-11

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