JPS5792837A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5792837A
JPS5792837A JP16937380A JP16937380A JPS5792837A JP S5792837 A JPS5792837 A JP S5792837A JP 16937380 A JP16937380 A JP 16937380A JP 16937380 A JP16937380 A JP 16937380A JP S5792837 A JPS5792837 A JP S5792837A
Authority
JP
Japan
Prior art keywords
layer
etching
impurity
windows
prescribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16937380A
Other languages
Japanese (ja)
Other versions
JPS6367331B2 (en
Inventor
Shigeru Komatsu
Michio Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16937380A priority Critical patent/JPS5792837A/en
Publication of JPS5792837A publication Critical patent/JPS5792837A/en
Publication of JPS6367331B2 publication Critical patent/JPS6367331B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To enable to perform etching of a semiconductor device with high precision in the simplified manufacturing process by a method wherein the difference of etching speed between insulating layers is enlarged by the heat treatment process. CONSTITUTION:The insulating layers 11, 12 are formed in the prescribed regions of a semiconductor substrate 10. An impurity layer 11 is formed by ion implantation of the prescribed conductive impurity through the layer 12. A resist film 14 having a window 14a is formed, and a high concentration impurity layer 15 is formed through the window 14a. After the film 14 is removed, heat treatment is performed to the substrate 10 at 700 deg.C or more. The insulating layer 16 is accumulated on the layers 11, 12 by the vapor phase epitaxial growth method. Windows 16a, 16b are formed in the layer 16 to expose the layer 12. Because the layer 12 is implanted with an impurity and is sintered, the layer thereof has the etching speed being much slower than the layer 16. Accordingly, when the windows 16a, 16b are to be formed, the layer 12 being directly under the layer 16 is prevented from etching to enable to form the windows 16a, 16b to the prescribed depth, and moreover, the layer 15 can be prevented from etching in the afterward process.
JP16937380A 1980-12-01 1980-12-01 Manufacture of semiconductor device Granted JPS5792837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16937380A JPS5792837A (en) 1980-12-01 1980-12-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16937380A JPS5792837A (en) 1980-12-01 1980-12-01 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5792837A true JPS5792837A (en) 1982-06-09
JPS6367331B2 JPS6367331B2 (en) 1988-12-26

Family

ID=15885383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16937380A Granted JPS5792837A (en) 1980-12-01 1980-12-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5792837A (en)

Also Published As

Publication number Publication date
JPS6367331B2 (en) 1988-12-26

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