JPS5789105A - Timer device - Google Patents

Timer device

Info

Publication number
JPS5789105A
JPS5789105A JP16731680A JP16731680A JPS5789105A JP S5789105 A JPS5789105 A JP S5789105A JP 16731680 A JP16731680 A JP 16731680A JP 16731680 A JP16731680 A JP 16731680A JP S5789105 A JPS5789105 A JP S5789105A
Authority
JP
Japan
Prior art keywords
output
circuit
address
counter
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16731680A
Other languages
Japanese (ja)
Inventor
Tsutomu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16731680A priority Critical patent/JPS5789105A/en
Publication of JPS5789105A publication Critical patent/JPS5789105A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/07—Programme control other than numerical control, i.e. in sequence controllers or logic controllers where the programme is defined in the fixed connection of electrical elements, e.g. potentiometers, counters, transistors

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)

Abstract

PURPOSE:To decrease the number of circuit elements even in case when a number of timers are required, by previously storing N types of preset data and start flags in a storage circuit. CONSTITUTION:The data of an address (i) in a start flag storage region 10a is read in the first period and set to a start flag storage circuit 4. At the same time, the numerical data of an address (i) in a count value storage region 10b is read and set to a subtractor counter 6. In the next period, an output of a decoder 15c is set at a high level, and an AND gate 14 allows the passing of the clock sent from a clock input terminal only for this period. Thus the counter 6 receives the subtraction of 1. This action is repeated to set the contents of the counter to 0, and accordingly the output of a time-up detecting circuit 7 is set at a high level to be stored in an ON flag storage circuit 8. In this case, the other output of the decoder 15c is set at a low level and in a write mode, and the output of the circuit 8 is written into an address (i) in an ON flag region 10c.
JP16731680A 1980-11-25 1980-11-25 Timer device Pending JPS5789105A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16731680A JPS5789105A (en) 1980-11-25 1980-11-25 Timer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16731680A JPS5789105A (en) 1980-11-25 1980-11-25 Timer device

Publications (1)

Publication Number Publication Date
JPS5789105A true JPS5789105A (en) 1982-06-03

Family

ID=15847483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16731680A Pending JPS5789105A (en) 1980-11-25 1980-11-25 Timer device

Country Status (1)

Country Link
JP (1) JPS5789105A (en)

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