JPS5616894A - Electronic timer unit - Google Patents

Electronic timer unit

Info

Publication number
JPS5616894A
JPS5616894A JP9216579A JP9216579A JPS5616894A JP S5616894 A JPS5616894 A JP S5616894A JP 9216579 A JP9216579 A JP 9216579A JP 9216579 A JP9216579 A JP 9216579A JP S5616894 A JPS5616894 A JP S5616894A
Authority
JP
Japan
Prior art keywords
signal
circuit
address
terminal
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9216579A
Other languages
Japanese (ja)
Inventor
Yuji Nakamae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9216579A priority Critical patent/JPS5616894A/en
Publication of JPS5616894A publication Critical patent/JPS5616894A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to perform the function similar to plural timers with one timer, by operating and controlling a control object corresponding to the address when the set time of a memory element agrees with the time signal of the timer counting part.
CONSTITUTION: For example, time 3ms is written into memory element 2a through time write terminal 1a. Meanwhile, when the clock signal of period 1ms comes to terminal 3, timer counting part 4 supplies the time signal of 1ms to comparing circuit 10. The clock signal is input to reset terminal R of address generating circuit 5 also, and the 0 address signal is output from circuit 5. Then, the gate of address agreement circuit 11a opens, and the set time 3ms of element 2a is compared with the signal of 1ms from counting part 4 by circuit 10. As the result, the disagreement signal is given to circuit 5, and the address of circuit 5 is counted up. Similar comparison is performed for all addresses. When the third clock signal is input to terminal 3, the signal agress with storage of element 2a in circuit 11a, and the agreement signal is output from terminal 12.
COPYRIGHT: (C)1981,JPO&Japio
JP9216579A 1979-07-20 1979-07-20 Electronic timer unit Pending JPS5616894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9216579A JPS5616894A (en) 1979-07-20 1979-07-20 Electronic timer unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9216579A JPS5616894A (en) 1979-07-20 1979-07-20 Electronic timer unit

Publications (1)

Publication Number Publication Date
JPS5616894A true JPS5616894A (en) 1981-02-18

Family

ID=14046808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9216579A Pending JPS5616894A (en) 1979-07-20 1979-07-20 Electronic timer unit

Country Status (1)

Country Link
JP (1) JPS5616894A (en)

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