JPS5654646A - Control circuit of tape recorder - Google Patents
Control circuit of tape recorderInfo
- Publication number
- JPS5654646A JPS5654646A JP13050279A JP13050279A JPS5654646A JP S5654646 A JPS5654646 A JP S5654646A JP 13050279 A JP13050279 A JP 13050279A JP 13050279 A JP13050279 A JP 13050279A JP S5654646 A JPS5654646 A JP S5654646A
- Authority
- JP
- Japan
- Prior art keywords
- mode
- switch
- reproduction
- counter
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To ensure an assured mode control for a tape recorder with no malfunction, by giving a mode switch control including the switch blocking for a fixed time by the switch which is closed via the tape counter.
CONSTITUTION: When the rewinding is carried out to set the count value of the tape counter to 0, the switch is closed to invert the switching transistor 2 into the conduction. And the output of the OR circuit 7 is inverted to a low level. The tape recorder is switched to the reproduction mode by the low-level output mentioned above, and at the same time the mono-multi 12 delivers a high-level pulse of a fixed duration with the trigger given from the reproduction output terminal. Thus the output of the OR circuit 6 is inverted to a high level for a fixed time. As a result, the reproduction mode is secured after the count value of the counter becomes 0 by the inertia. And immediately after this, the count value of the counter vecomes 0 again to block the mode switching although the switch 1 may be closed. As a result, a switching is secured assuredly from rewinding to reproduction with no malfunction. The other mode switchings are also carried out in the same way.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54130502A JPS6042534B2 (en) | 1979-10-09 | 1979-10-09 | Tape recorder control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54130502A JPS6042534B2 (en) | 1979-10-09 | 1979-10-09 | Tape recorder control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5654646A true JPS5654646A (en) | 1981-05-14 |
JPS6042534B2 JPS6042534B2 (en) | 1985-09-24 |
Family
ID=15035798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54130502A Expired JPS6042534B2 (en) | 1979-10-09 | 1979-10-09 | Tape recorder control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6042534B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57164844U (en) * | 1981-04-14 | 1982-10-18 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60102902U (en) * | 1983-12-20 | 1985-07-13 | 北川機械工業株式会社 | Numerical control router table device for woodworking |
DE3522829A1 (en) * | 1985-06-26 | 1987-01-02 | Hell Rudolf Dr Ing Gmbh | Vacuum clamping plate with automatic format adaptation |
TWI416665B (en) * | 2011-02-01 | 2013-11-21 | Inotera Memories Inc | Vertical transistor of random access memory and manufacturing method thereof |
-
1979
- 1979-10-09 JP JP54130502A patent/JPS6042534B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57164844U (en) * | 1981-04-14 | 1982-10-18 |
Also Published As
Publication number | Publication date |
---|---|
JPS6042534B2 (en) | 1985-09-24 |
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