JPS56145402A - Sequence controller - Google Patents
Sequence controllerInfo
- Publication number
- JPS56145402A JPS56145402A JP4689180A JP4689180A JPS56145402A JP S56145402 A JPS56145402 A JP S56145402A JP 4689180 A JP4689180 A JP 4689180A JP 4689180 A JP4689180 A JP 4689180A JP S56145402 A JPS56145402 A JP S56145402A
- Authority
- JP
- Japan
- Prior art keywords
- time interval
- period
- flag
- controlled system
- interruption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/07—Programme control other than numerical control, i.e. in sequence controllers or logic controllers where the programme is defined in the fixed connection of electrical elements, e.g. potentiometers, counters, transistors
Abstract
PURPOSE:To bring a controlled system, which has an input short or long in the on time of a contact, under the control of one sequence controller, by discriminating the time interval of a timer interruption from the most significant digit bit flag of the starting address in a memory. CONSTITUTION:The output of oscillator 10 is frequency-divided by counter 10 to generate pulse signal S1 of 5ms, for example, in time interval, which is further frequency-divided by poststage counter 11 to generate pulse signal S2 of 30ms in time interval. As for period-selecting flags for a table in a memory, the flag which actuates the most significant digit bit of the starting address of each block in 5ms is set to ''1'', and the flag starting it in 30ms is also set to ''0''. Only when a processor is to read the period of a timer interruption, an input signal to gate terminal G is held at the low level and which interruption time interval is the corresponding interruption of the timer interruption period is discriminated and fetched in the processor. Consequently, a controlled system which has an input short in the ON time of a contact or requires a high processing rate and another controlled system are brough under the sequence control of one controller.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4689180A JPS56145402A (en) | 1980-04-11 | 1980-04-11 | Sequence controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4689180A JPS56145402A (en) | 1980-04-11 | 1980-04-11 | Sequence controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56145402A true JPS56145402A (en) | 1981-11-12 |
Family
ID=12759976
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4689180A Pending JPS56145402A (en) | 1980-04-11 | 1980-04-11 | Sequence controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56145402A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60225904A (en) * | 1984-04-24 | 1985-11-11 | Omron Tateisi Electronics Co | Programmable controller |
US4955360A (en) * | 1987-04-10 | 1990-09-11 | Nippon Steel Corporation | Heat-generating material for portable hair curler |
-
1980
- 1980-04-11 JP JP4689180A patent/JPS56145402A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60225904A (en) * | 1984-04-24 | 1985-11-11 | Omron Tateisi Electronics Co | Programmable controller |
US4955360A (en) * | 1987-04-10 | 1990-09-11 | Nippon Steel Corporation | Heat-generating material for portable hair curler |
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