JPS5794988A - Refreshment control circuit - Google Patents

Refreshment control circuit

Info

Publication number
JPS5794988A
JPS5794988A JP55171600A JP17160080A JPS5794988A JP S5794988 A JPS5794988 A JP S5794988A JP 55171600 A JP55171600 A JP 55171600A JP 17160080 A JP17160080 A JP 17160080A JP S5794988 A JPS5794988 A JP S5794988A
Authority
JP
Japan
Prior art keywords
refreshment
address
counter
request
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55171600A
Other languages
Japanese (ja)
Inventor
Katsumi Fujinami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55171600A priority Critical patent/JPS5794988A/en
Publication of JPS5794988A publication Critical patent/JPS5794988A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To set the best refreshment cycles without reference to the cycles of a clock input, by optionally varying the cycles of a counter, which sets the refreshment cycles, according to input conditions. CONSTITUTION:A counter 2 counts up with a system clock 6 to output a count signal 8, and a coincidence detection part 3 detects the coincidence between the count signal 8 and a refreshment cycle setting signal 9 to output a refreshment request 10. Once the request 10 is outputted, a counter part 1 is reset while an address counter 4 is made to count up. Therefore, the request 10 is a one-cycle signal synchronizing with the clock 6, and the counter part 1 is enabled by the signal 9 to set the cycle of the request 10 to an optional value. Then, the counter 4 counts up in response to the request 10 to output a refreshment address 1 to an address selection part 5 and when an address 11 and an external address 7 are inputted and a refreshment instruction 12 is supplied, the address is selected as a substitute for the external address 7, thereby outputting a signal 13.
JP55171600A 1980-12-05 1980-12-05 Refreshment control circuit Pending JPS5794988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55171600A JPS5794988A (en) 1980-12-05 1980-12-05 Refreshment control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55171600A JPS5794988A (en) 1980-12-05 1980-12-05 Refreshment control circuit

Publications (1)

Publication Number Publication Date
JPS5794988A true JPS5794988A (en) 1982-06-12

Family

ID=15926165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55171600A Pending JPS5794988A (en) 1980-12-05 1980-12-05 Refreshment control circuit

Country Status (1)

Country Link
JP (1) JPS5794988A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336838B1 (en) * 1999-06-17 2002-05-16 윤종용 Dynamic random access memory device with refresh period selecting circuit and input/output bit width selecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336838B1 (en) * 1999-06-17 2002-05-16 윤종용 Dynamic random access memory device with refresh period selecting circuit and input/output bit width selecting circuit

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