JPS5715547A - Data receiver - Google Patents
Data receiverInfo
- Publication number
- JPS5715547A JPS5715547A JP9042380A JP9042380A JPS5715547A JP S5715547 A JPS5715547 A JP S5715547A JP 9042380 A JP9042380 A JP 9042380A JP 9042380 A JP9042380 A JP 9042380A JP S5715547 A JPS5715547 A JP S5715547A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- counter
- output
- timing
- start signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Selective Calling Equipment (AREA)
Abstract
PURPOSE:To correct the timing of data read-in automatically, by counting the basic clock through the detection of the l-th bit of a start signal and controlling the number of stages of a number of stage variable ring counter with this output. CONSTITUTION:When the l-th bit of a start signal of a serial binary code consisting of the start signal and a data signal for one frame is detected at an l-th bit detecting circuit 22, the output is at 1 and the output of a basic clock oscillator 21 is introduced to a counter 24 via an AND circuit 23. The content of the counter 24 is inputted to a decoder 25 and the number of stage of a number of stage variable ring counter 26 is controlled according to one bit period of the l-th bit of the input serial binary code. Thus, the timing clock being the output of the counter 26 changes the phase of production in response to the length of the one bit period and the data read-in timing pulse can be obtained at the center of each bit of the data signal from a timing pulse generating circuit 27.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9042380A JPS5715547A (en) | 1980-07-02 | 1980-07-02 | Data receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9042380A JPS5715547A (en) | 1980-07-02 | 1980-07-02 | Data receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5715547A true JPS5715547A (en) | 1982-01-26 |
Family
ID=13998189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9042380A Pending JPS5715547A (en) | 1980-07-02 | 1980-07-02 | Data receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5715547A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63224945A (en) * | 1987-03-03 | 1988-09-20 | ダブリユー・アール・グレイス・アンド・カンパニー−コネチカツト | Thermoplastic multilayer barriering packaging film and bags manufactured from said film |
| JP2020080877A (en) * | 2018-11-14 | 2020-06-04 | 株式会社ニューギン | Game machine |
-
1980
- 1980-07-02 JP JP9042380A patent/JPS5715547A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63224945A (en) * | 1987-03-03 | 1988-09-20 | ダブリユー・アール・グレイス・アンド・カンパニー−コネチカツト | Thermoplastic multilayer barriering packaging film and bags manufactured from said film |
| JP2020080877A (en) * | 2018-11-14 | 2020-06-04 | 株式会社ニューギン | Game machine |
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