JPS56140598A - Error control system of memory device - Google Patents

Error control system of memory device

Info

Publication number
JPS56140598A
JPS56140598A JP4172180A JP4172180A JPS56140598A JP S56140598 A JPS56140598 A JP S56140598A JP 4172180 A JP4172180 A JP 4172180A JP 4172180 A JP4172180 A JP 4172180A JP S56140598 A JPS56140598 A JP S56140598A
Authority
JP
Japan
Prior art keywords
error
counter
signal
circuit
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4172180A
Other languages
Japanese (ja)
Inventor
Ryuichi Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4172180A priority Critical patent/JPS56140598A/en
Publication of JPS56140598A publication Critical patent/JPS56140598A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To utilize effectively a memory device having defection, by enabling an error within a permissible limit to be processed continuously by providing an error frequency counting means and comparing means. CONSTITUTION:An error signal outputted from read control circuit 3 is inputted to error control circuit 5. At time 1 in the figure, counter 30 of circuit 5 is reset. Next, as the error signal is generated once at some time 2 corresponding to the occurrence of a read error, the value of counter 30 becomes ''1''. Similarly, the error signal is outputted (n) times up to a certain time and counter 30 goes up to (n); if it is greater than error permissible frequency N held in constant holding register 31 of circuit 5, comparing circuit 32 outputs an error over signal. On the other hand, if N is greater than (n), namely, if it is within the error-occurrence permissible limit, counter 30 is reset with the output signal of timer 4 at time 3 in the figure and repeats the said operation again. In this case, no error over signal is generated, so that the data processing will be continued.
JP4172180A 1980-03-31 1980-03-31 Error control system of memory device Pending JPS56140598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4172180A JPS56140598A (en) 1980-03-31 1980-03-31 Error control system of memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4172180A JPS56140598A (en) 1980-03-31 1980-03-31 Error control system of memory device

Publications (1)

Publication Number Publication Date
JPS56140598A true JPS56140598A (en) 1981-11-02

Family

ID=12616276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4172180A Pending JPS56140598A (en) 1980-03-31 1980-03-31 Error control system of memory device

Country Status (1)

Country Link
JP (1) JPS56140598A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111887U (en) * 1982-01-26 1983-07-30 平野　道仁 refrigerator
US4941161A (en) * 1987-04-14 1990-07-10 Hewlett-Packard Company Detection of digital signal error rates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111887U (en) * 1982-01-26 1983-07-30 平野　道仁 refrigerator
US4941161A (en) * 1987-04-14 1990-07-10 Hewlett-Packard Company Detection of digital signal error rates

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