JPS56140598A - Error control system of memory device - Google Patents
Error control system of memory deviceInfo
- Publication number
- JPS56140598A JPS56140598A JP4172180A JP4172180A JPS56140598A JP S56140598 A JPS56140598 A JP S56140598A JP 4172180 A JP4172180 A JP 4172180A JP 4172180 A JP4172180 A JP 4172180A JP S56140598 A JPS56140598 A JP S56140598A
- Authority
- JP
- Japan
- Prior art keywords
- error
- counter
- signal
- circuit
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To utilize effectively a memory device having defection, by enabling an error within a permissible limit to be processed continuously by providing an error frequency counting means and comparing means. CONSTITUTION:An error signal outputted from read control circuit 3 is inputted to error control circuit 5. At time 1 in the figure, counter 30 of circuit 5 is reset. Next, as the error signal is generated once at some time 2 corresponding to the occurrence of a read error, the value of counter 30 becomes ''1''. Similarly, the error signal is outputted (n) times up to a certain time and counter 30 goes up to (n); if it is greater than error permissible frequency N held in constant holding register 31 of circuit 5, comparing circuit 32 outputs an error over signal. On the other hand, if N is greater than (n), namely, if it is within the error-occurrence permissible limit, counter 30 is reset with the output signal of timer 4 at time 3 in the figure and repeats the said operation again. In this case, no error over signal is generated, so that the data processing will be continued.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4172180A JPS56140598A (en) | 1980-03-31 | 1980-03-31 | Error control system of memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4172180A JPS56140598A (en) | 1980-03-31 | 1980-03-31 | Error control system of memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56140598A true JPS56140598A (en) | 1981-11-02 |
Family
ID=12616276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4172180A Pending JPS56140598A (en) | 1980-03-31 | 1980-03-31 | Error control system of memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56140598A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58111887U (en) * | 1982-01-26 | 1983-07-30 | 平野 道仁 | refrigerator |
US4941161A (en) * | 1987-04-14 | 1990-07-10 | Hewlett-Packard Company | Detection of digital signal error rates |
-
1980
- 1980-03-31 JP JP4172180A patent/JPS56140598A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58111887U (en) * | 1982-01-26 | 1983-07-30 | 平野 道仁 | refrigerator |
US4941161A (en) * | 1987-04-14 | 1990-07-10 | Hewlett-Packard Company | Detection of digital signal error rates |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5345120A (en) | Video special effect device | |
JPS56140598A (en) | Error control system of memory device | |
JPS5636702A (en) | Terminal control system of sequence controller | |
JPS5554403A (en) | Zero adjuster | |
JPS5499540A (en) | Malfunction detecting device for electronic circuit | |
JPS5727322A (en) | Input and output controlling system of computer | |
JPS5787232A (en) | Input signal reading circuit | |
JPS5424553A (en) | Control system for data transfer | |
JPS56114441A (en) | Counting circuit | |
JPS56137450A (en) | Runaway detection and returning device of operation processor | |
JPS54138975A (en) | Position pulse correcting circuit | |
JPS57201889A (en) | Electronic watch with data input function | |
JPS55123740A (en) | Information processing unit | |
JPS5690500A (en) | Semiconductor memory device | |
JPS53141448A (en) | Logical operation circuit | |
JPS52128028A (en) | Universal timing control method of data processing unit | |
JPS5713543A (en) | Data speed transducer | |
JPS5699528A (en) | Timer device of computer system | |
JPS5422137A (en) | Bus line chekcing device | |
JPS56103743A (en) | Microprogram controller | |
JPS57187729A (en) | Input module device | |
JPS5663625A (en) | Timer circuit | |
JPS57111759A (en) | Data transfer fault detecting system | |
JPS5624592A (en) | Time setting system | |
JPS5423948A (en) | Inspection system for digital protective device |