JPS5690328A - Keyboard control system - Google Patents

Keyboard control system

Info

Publication number
JPS5690328A
JPS5690328A JP16775879A JP16775879A JPS5690328A JP S5690328 A JPS5690328 A JP S5690328A JP 16775879 A JP16775879 A JP 16775879A JP 16775879 A JP16775879 A JP 16775879A JP S5690328 A JPS5690328 A JP S5690328A
Authority
JP
Japan
Prior art keywords
matrix
key
contents
cpu8
counters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16775879A
Other languages
Japanese (ja)
Inventor
Takatoshi Ishii
Haruhiko Tomono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16775879A priority Critical patent/JPS5690328A/en
Publication of JPS5690328A publication Critical patent/JPS5690328A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make the keyboard for scanning the matrix have the N-key roll-over function, by providing two buffers for detecting a variation of the key code, and processing the contents as an input data in case when the memory contents of said buffers are same.
CONSTITUTION: The key matrix 1 is scanned by the outputs of the counters 4, 5 for counting the clock pulse of the oscillating circuit 6, and when the key switch of the matrix 1 has been depressed, the output of the matrix 1 is detected by the selector 3. Counting of the counters 4, 5 is stopped by said detected output, also a signal as keyboard status is output to the CPU8, and the counting values of the counters 4, 5 are input to the storage device 9. To this storage device 9 is connected the CPU8, and also two buffer registers 10, 11 are installed to the storage device 9. And, plural key codes which have been depressed at the same time by the CPU8 are read by different timing from the registers 10, 11, and in case when the contents are same, the storage contents are processed as an input data.
COPYRIGHT: (C)1981,JPO&Japio
JP16775879A 1979-12-24 1979-12-24 Keyboard control system Pending JPS5690328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16775879A JPS5690328A (en) 1979-12-24 1979-12-24 Keyboard control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16775879A JPS5690328A (en) 1979-12-24 1979-12-24 Keyboard control system

Publications (1)

Publication Number Publication Date
JPS5690328A true JPS5690328A (en) 1981-07-22

Family

ID=15855539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16775879A Pending JPS5690328A (en) 1979-12-24 1979-12-24 Keyboard control system

Country Status (1)

Country Link
JP (1) JPS5690328A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168136A (en) * 1982-03-29 1983-10-04 Fujitsu Ltd Keyboard controlling circuit
JPS6132127A (en) * 1984-07-24 1986-02-14 Alps Electric Co Ltd Key output system of keyboard

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168136A (en) * 1982-03-29 1983-10-04 Fujitsu Ltd Keyboard controlling circuit
JPS6132127A (en) * 1984-07-24 1986-02-14 Alps Electric Co Ltd Key output system of keyboard
JPH051485B2 (en) * 1984-07-24 1993-01-08 Alps Electric Co Ltd

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