JPS5776864A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5776864A JPS5776864A JP15313680A JP15313680A JPS5776864A JP S5776864 A JPS5776864 A JP S5776864A JP 15313680 A JP15313680 A JP 15313680A JP 15313680 A JP15313680 A JP 15313680A JP S5776864 A JPS5776864 A JP S5776864A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring layer
- wiring
- contact
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To improve the degree of integration of an integrated circuit by forming a trapezoid polysilicon layer, the surface thereof is oxidized, under the first wiring layer of section where the first wiring layer and the second wiring layer separated by a layer insulating layer contact. CONSTITUTION:When the first wiring layers 1, 11 are shaped onto a lower layer insulating layer 4 formed onto a semiconductor substrate not shown and the second wiring layer 21 and a cover glass layer 24 are molded through an upper layer phosphours-silicon-glass layer 14, the trapezoid polysilicon layer 6, the surface thereof has an oxide film 6', is formed under the section where the first wiring layer 1 and the second wiring layer 21 contact. Accordingly, the second wiring layer can be shaped positively even when the positions of through-holes for contact are displaced, and the degree of integration is also improved because the contact forming section need not be magnified and molded.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15313680A JPS5776864A (en) | 1980-10-31 | 1980-10-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15313680A JPS5776864A (en) | 1980-10-31 | 1980-10-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5776864A true JPS5776864A (en) | 1982-05-14 |
Family
ID=15555783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15313680A Pending JPS5776864A (en) | 1980-10-31 | 1980-10-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5776864A (en) |
-
1980
- 1980-10-31 JP JP15313680A patent/JPS5776864A/en active Pending
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