JPS5756959A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5756959A
JPS5756959A JP55132147A JP13214780A JPS5756959A JP S5756959 A JPS5756959 A JP S5756959A JP 55132147 A JP55132147 A JP 55132147A JP 13214780 A JP13214780 A JP 13214780A JP S5756959 A JPS5756959 A JP S5756959A
Authority
JP
Japan
Prior art keywords
layer
wording
wire
polysilicon
fets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55132147A
Other languages
Japanese (ja)
Inventor
Shiyouji Ariizumi
Makoto Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55132147A priority Critical patent/JPS5756959A/en
Priority to EP81304319A priority patent/EP0048610B1/en
Priority to DE8181304319T priority patent/DE3173506D1/en
Publication of JPS5756959A publication Critical patent/JPS5756959A/en
Priority to US06/814,295 priority patent/US4673969A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To accelerate a static MOSRAM and to simplify the steps of manufacture the MOSRAM by forming a low resistance part to become a wording wire and a high resistance part to become a resistance element connected in parallel with the first layer at the second layer polysilicon in a two-layer polysilicon structure. CONSTITUTION:Two-layer polystructure is formed in a memory cell made of FETs Q1-Q4 and resistors R1, R2. The gate electrodes and wording wires W of the FETs Q1-Q4 are formed of the first polysilicon 4, and the second polylayer 6 is formed through an insulating film 5. A region pattern to superpose with the wording wire W of the second layer 6 is doped in low resistance, and is connected in parallel with the first layer 4 with a plurality of contacts 21. The region not superposed with the wording wire W is formed by patterning the resistors R1, R2 as high resistance. Then, an insulating film is formed on the overall surface, an aluminum wire 13 is formed, to complete a cell circuit. In this manner, the resistance value of the wording wire W can be reduced to approx. 1/2, and the cell configuration can be simplified.
JP55132147A 1980-09-22 1980-09-22 Semiconductor device and manufacture thereof Pending JPS5756959A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP55132147A JPS5756959A (en) 1980-09-22 1980-09-22 Semiconductor device and manufacture thereof
EP81304319A EP0048610B1 (en) 1980-09-22 1981-09-21 Semiconductor device and its manufacture
DE8181304319T DE3173506D1 (en) 1980-09-22 1981-09-21 Semiconductor device and its manufacture
US06/814,295 US4673969A (en) 1980-09-22 1985-12-30 Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55132147A JPS5756959A (en) 1980-09-22 1980-09-22 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5756959A true JPS5756959A (en) 1982-04-05

Family

ID=15074449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55132147A Pending JPS5756959A (en) 1980-09-22 1980-09-22 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5756959A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62287644A (en) * 1986-06-06 1987-12-14 Nec Corp Semiconductor integrated device
CN1315189C (en) * 2003-05-06 2007-05-09 旺宏电子股份有限公司 Character line interface point arranging structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55120150A (en) * 1979-03-09 1980-09-16 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55120150A (en) * 1979-03-09 1980-09-16 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62287644A (en) * 1986-06-06 1987-12-14 Nec Corp Semiconductor integrated device
CN1315189C (en) * 2003-05-06 2007-05-09 旺宏电子股份有限公司 Character line interface point arranging structure

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