JPS62287644A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To manufacture AD converters with high accuracy by a method wherein upper layer interconnection pattern extention parts including the second layer are throughhole-connected to the first layer extention part. CONSTITUTION:An interconnection pattern 4 is provided with interconnection pattern extention parts 5 on the parts extended from the rows of respective comparators 3. A silicon dioxide insulating layer 8 is provided on a silicon substrate 1 while the interconnection pattern 4, the first layer extention 5A and interconnection pattern connecting parts 7 are provided on the insulating layer 8. The second layer extention part 5B is provided through the intermediary of another insulating layer 9 to be connected to the first layer extention part 5A by a through hole 6. Through these procedures, in parallel comparison type AD converters with higher integrity can be manufactured. Furthermore, the converters as multilayered structure may be connected via extention parts thereof by means of through-holes.

Description

[Detailed Description of the Invention] & Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated device, particularly a high-resolution parallel comparison type A.
The present invention relates to a semiconductor integrated device that constitutes a D converter.

[Prior Art] Conventionally, when a parallel comparison type AD converter is constructed using a semiconductor integrated device, a plurality of comparators are arranged on a semiconductor substrate, and in order to apply a reference voltage to each comparator, these comparators are A wiring pattern of a certain width is provided in parallel with the rows of , a certain section length of this wiring pattern is used as a reference resistor, and a wiring pattern for connection with each comparator is provided for each certain section length of this pattern. ing. By the way, if the resolution of this converter is n bits, it has 2-1 comparators and 2
In high-resolution converters, it is difficult to arrange all the comparators and the wiring pattern for the reference resistor in a straight line, so it is necessary to arrange the wiring pattern for each comparator in a folded manner. I'm taking it. In addition, in this folded arrangement, in order to provide the output of each comparator to the encoder section with as little delay time as possible, the encoder section is placed between the rows of comparators, and the wiring pattern for the reference resistor is set to 2. It is provided outside the row of comparators arranged in a row. For this reason, the length of the wiring pattern at the folded part connecting these two rows of wiring patterns becomes extremely long, and in order to make the resistance value of this part equal to the reference resistance value, the length of the wiring pattern is much longer than that of the above-mentioned constant width wiring pattern. In order to connect with a wide wiring pattern or to equalize the resistance value deviation during manufacturing, a large number of wiring patterns of a certain width are provided in parallel and connected. [Problem to be solved by the invention] However, In the above-mentioned conventional semiconductor integrated device of the AD converter, the resistance of the folded portion is determined from the resistance of the extended portion of the wiring pattern of a constant width parallel to the comparator and the resistance of the wiring pattern connection portion that connects the extended portion. Therefore, in order to make the resistance of the folded part equal to the reference resistance, the width of the wiring pattern connection part must be made extremely wide, or if the wiring pattern is connected with a fixed width as described above, it must be extended as the number of parallel wires increases. The part becomes longer, and the resistance of that part is added, so the resistance value does not decrease as much as the number of parallel lines increases, and it occupies a large area on the board, so the degree of integration does not improve by that much. There are problems.

An object of the present invention is to eliminate the above-mentioned problems and to provide a semiconductor integrated device comprising a parallel comparison type AD converter with an improved degree of integration by reducing the area of the folded portion.

[Means for solving problems]

The present invention consists of a linear wiring pattern of a constant width that is used as a reference resistor, and a large number of comparators arranged in line with this wiring pattern. The integrated device has a multilayer structure in which wiring patterns of wiring pattern extensions that connect respective ends of the adjacent wiring patterns are connected by through holes.

Further, the first layer wiring pattern width of the wiring pattern extension portion is the above-mentioned constant width, and the width of the multi-layer wiring pattern extension portion connected by the through hole is wider than the above-mentioned certain width.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(2) is a plan view of one embodiment of the present invention, showing a case where the wiring pattern extension part has a two-layer structure.

In the figure, a plurality of comparators 3 are provided in two rows on a silicon substrate 1 with an encoder section 2 in between. A wiring pattern 4 of Newum is provided. A certain length of this wiring pattern 4 is used as a reference resistance, and in order to provide a reference voltage to each comparator 3, a wiring pattern for connection with each comparator 3 is provided for each certain length of this pattern 4. are doing. Further, the wiring pattern 4 has a wiring pattern extension part 5 in a portion outside the row of each comparator 3, and the wiring pattern 4
A wiring pattern connecting portion 7 consisting of a plurality of wiring patterns having approximately the same width as the wiring pattern connecting portion 7 connects between the wiring pattern extension portions 5 to form a reference resistance. Furthermore, the wiring pattern extension part 5 has a two-layer structure, and the first layer extension part 5A and the second layer extension part 5B of the wiring pattern extension part 5 are connected by a through hole 6.

FIG. 1 (■) is a cross-sectional view taken along the Y-Y- line in FIG. A first layer extension part 5A and a wiring pattern connection part 7 of the section 5 are provided, and a second layer extension part 5B is provided thereon via an insulating layer 9 made by CVD method or the like. It is shown that the first layer extension part 5A and the second layer extension part 5B are connected by a through hole 6.

In the above embodiments, the wiring pattern extensions have a two-layer structure, but they may also have a multilayer structure and all of these extensions may be connected by through holes.

Further, in the above embodiments, the wiring pattern is made of aluminum, but there is no restriction at all that it may be made of other conductive materials.

[Effects of the Invention] As explained in detail above, the present invention provides a multilayer structure for the wiring pattern extension part of the folded part, by widening the pattern width of the upper layer extension part including the second color, and increasing the pattern width of the upper layer extension part including the second color. By making through-hole connections with the wiring pattern extensions, the equivalent resistance of the wiring pattern extensions can be significantly reduced, and the number of parallel wiring patterns in the wiring pattern connection parts that connect the extensions can be reduced, reducing the area of the folded parts. Can be made smaller. In addition, by significantly reducing the resistance of the wiring pattern extension, even if there is a uniform deviation in the finished width of the wiring pattern during the manufacturing process, the standard resistance of the straight wiring pattern and the wiring pattern connection part of the folded part can be easily adjusted. The effect is that the ratio with the resistance can be matched, and a highly accurate AD converter can be realized.

Furthermore, even when the wiring pattern connection part is composed of a single wide wiring pattern, by making the wiring pattern extension part have a multilayer structure, the resistance of this extension part can be significantly lowered. This has the advantage that the reference resistance can be set based on the pattern width of the area.

[Brief explanation of drawings]

Figure 1 (at is a plan view of one embodiment of the present invention, Figure 1 (h
is a sectional view of a portion of FIG. 1(a). 2... Encoder section, 3... Comparator. 4... Wiring pattern (for reference resistance). 5...Wiring pattern extension part. 5A...First layer extension. 5b...Second layer extension. 6...Through hole. 7... Wiring pattern connection part. 9...Insulating layer.

Claims (2)

[Claims] (1) A semiconductor that configures one AD converter by arranging a linear wiring pattern of a constant width used as a reference resistor and a number of comparators arranged in line with this wiring pattern as a set. 1. A semiconductor integrated device, characterized in that the wiring patterns of the wiring pattern extensions connecting the respective ends of the adjacent wiring patterns have a multilayer structure in which each wiring pattern is connected by a through hole. (2) The width of the wiring pattern of the first layer of the wiring pattern extension part is the above-mentioned constant width, and the width of the wiring pattern extension part connected by the through hole is wider than the above-mentioned certain width. The semiconductor integrated device according to item 1.