JPH0530072B2 - - Google Patents
Info
- Publication number
- JPH0530072B2 JPH0530072B2 JP10637084A JP10637084A JPH0530072B2 JP H0530072 B2 JPH0530072 B2 JP H0530072B2 JP 10637084 A JP10637084 A JP 10637084A JP 10637084 A JP10637084 A JP 10637084A JP H0530072 B2 JPH0530072 B2 JP H0530072B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- pattern
- voltage divider
- circuit
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は抵抗回路に係り、特に集積回路化に適
した抵抗分圧回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a resistor circuit, and more particularly to a resistor voltage divider circuit suitable for integration into an integrated circuit.
従来の半導体集積回路における抵抗素子として
は拡散層やポリシリコン，メタル配線層が用いら
れているが、第１図ａに示す抵抗分圧回路をアル
ミニウムのような低抵抗メタル配線層で構成する
場合は、第１図ｂのようなストリツプライン１０
から等間隔に分圧電圧端子１１を取り出したり、
第１図ｃのような櫛形のパターン１２を配置した
等間隔で分圧端子１３を引き出していたが、抵抗
分圧回路のパターン１０，１２が同図のように大
きく折り返される場合は斜線部１４，１５のよう
な不整合部分が生じる。これによる抵抗の誤差分
を補償するために、従来破線で囲まれるようなパ
ターンを設け、端子間ABの抵抗を調整する手法
がとられてきた。しかしこの調整には実際にいく
つかの補償パターンを集積回路で作製して実験評
価し、最適なパターンを求めるのがふつうであ
り、このために多くの手間と時間を要していた。
またシミユレーシヨンによつて最適なパターンを
求めることも可能であるが、実際には精度的な問
題も多く、テスト用の集積回路を作製して予備実
験を試みなければならないのが実情である。この
ことは集積回路で抵抗回路を設計する場合の大き
な欠点であつた。
Diffusion layers, polysilicon, and metal wiring layers are used as resistance elements in conventional semiconductor integrated circuits, but when the resistance voltage divider circuit shown in Figure 1a is constructed from a low-resistance metal wiring layer such as aluminum, is a stripline 10 as shown in Fig. 1b.
Take out the divided voltage terminals 11 at equal intervals from
The voltage dividing terminals 13 are drawn out at equal intervals with comb-shaped patterns 12 arranged as shown in FIG. , 15 occur. In order to compensate for the resistance error caused by this, conventional methods have been used to provide a pattern surrounded by a broken line and adjust the resistance between the terminals AB. However, this adjustment usually involves actually fabricating several compensation patterns using integrated circuits and experimentally evaluating them to find the optimal pattern, which requires a lot of effort and time.
It is also possible to find the optimal pattern through simulation, but in practice there are many problems with accuracy, and the reality is that it is necessary to fabricate integrated circuits for testing and conduct preliminary experiments. This has been a major drawback when designing resistor circuits with integrated circuits.
本発明の目的は上記の問題点を解決し、回路調
整することなく高精度が達成でき、集積回路化に
適した抵抗分圧回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a resistive voltage divider circuit that can achieve high accuracy without circuit adjustment and is suitable for integrated circuit implementation.
〔発明の概要〕
上記の目的を達成するため本発明では、抵抗配
線層のパターンを45゜の傾きをもつ部分配線パタ
ーンを接続して鋸歯状とし、これにより抵抗分圧
回路の折り返し部の不整合が生じないようにし
た。この結果従来の折り返し部のパターン調整が
不要になり、設計に手間どらず高精度な抵抗分圧
回路を実現できることがあきらかになつた。[Summary of the Invention] In order to achieve the above object, the present invention makes the pattern of the resistive wiring layer into a sawtooth shape by connecting partial wiring patterns having an inclination of 45°, thereby reducing the defects in the folded portion of the resistive voltage divider circuit. Prevented consistency from occurring. As a result, it has become clear that the conventional pattern adjustment of the folded portion is no longer necessary, and that a highly accurate resistor voltage divider circuit can be realized without any hassle in design.
以下、本発明の実施例を第２図〜第４図により
詳細に説明する。第２図は本発明の抵抗分圧回路
の配置パターン例を示す図である。幅Ｗのメタル
配線が±45゜傾きで互いに接続された鋸歯状に配
置されている。分圧電圧端子１１の隣合つた端子
間の平均的な長きは各端子の代表点Ｐの間の長さ
ｌで表わすことができる。各代表点間の長さｌは
すべて等しく、折り返し部についても成立つてい
ることがわかる。第２図で代表点P2とP1の間の
長さをｌ（P1−P2）で表わし、P1とPAおよびPAと
PBの間の長さをそれぞれｌ（PA−P1），ｌ（PB−
PA）とすると、
ｌ（PB−PA）＝ｌ（PA−P1）
＝ｌ（P1−P2）
となつている。つぎにこの鋸歯状配線に電流を流
した場合、配線幅Ｗに対し長さｌがある程度大き
くなると第２図に示す中間部分の断面Ｑの電流分
布は一様で互いに等しくなる。したがつて代表点
P2あるいはP1を含む配線のコーナ部の電流分布
とPAあるいはPBを含む配線のコーナ部の電流分
布は互いに等しいということができる。このこと
から分圧端子A2とA1，A1とＡ，ＡとＢの電圧は
互いに等しくなり、直線性のすぐれた分圧電圧が
得られる。従来の欠点であつた折り返し部の不整
合は除去することができ、回路調整が不要で高精
度の抵抗分圧回路を容易に設計することができ
る。
Embodiments of the present invention will be described in detail below with reference to FIGS. 2 to 4. FIG. 2 is a diagram showing an example of the arrangement pattern of the resistive voltage divider circuit of the present invention. Metal wires having a width W are arranged in a sawtooth shape connected to each other at an angle of ±45°. The average length between adjacent terminals of the divided voltage terminals 11 can be expressed by the length l between the representative points P of each terminal. It can be seen that the length l between each representative point is all equal, and this also holds true for the folded portion. In Figure 2, the length between the representative points P 2 and P 1 is expressed as l (P 1 − P 2 ), and P 1 and P A and P A
The lengths between P B are l(P A − P 1 ) and l(P B −
P A ), then l(P B −P A )=l(P A −P 1 )=l(P 1 −P 2 ). Next, when a current is passed through this sawtooth wiring, if the length l is increased to some extent with respect to the wiring width W, the current distribution in the cross section Q of the intermediate portion shown in FIG. 2 becomes uniform and equal to each other. Therefore, the representative point
It can be said that the current distribution in the corner portion of the wiring including P 2 or P 1 and the current distribution in the corner portion of the wiring including P A or P B are equal to each other. Therefore, the voltages at the voltage dividing terminals A 2 and A 1 , A 1 and A, and A and B are equal to each other, and a divided voltage with excellent linearity can be obtained. The mismatch in the folded portion, which was a conventional drawback, can be eliminated, and a highly accurate resistor voltage divider circuit can be easily designed without the need for circuit adjustment.
第３図は本発明の抵抗分圧回路の他の配置パタ
ーン例を示す図である。第２図と同様の鋸歯状配
線を用いているが、鋸歯状パターンのピツチを十
分小さくし、巨視的には第１図ｃに対応したパタ
ーンを構成している。折り返し部の端子Ａ，Ｂ間
の鋸歯状パターンの繰り返し数と一般の分圧端子
間A1，A2間のそれとは同数であり、図示の例で
は11となつている。第２図で述べた電流分布の一
様性の理由から第３図の抵抗分圧回路は折り返し
部においても所定の分圧電圧が得られ、直線性精
度のよい抵抗分圧回路が実現できる。 FIG. 3 is a diagram showing another example of the arrangement pattern of the resistive voltage divider circuit of the present invention. Although the same sawtooth wiring as in FIG. 2 is used, the pitch of the sawtooth pattern is made sufficiently small to constitute a pattern macroscopically corresponding to FIG. 1c. The number of repetitions of the sawtooth pattern between the terminals A and B of the folded portion is the same as that between the general voltage dividing terminals A 1 and A 2 , and is 11 in the illustrated example. Because of the uniformity of the current distribution described in FIG. 2, the resistor voltage divider circuit of FIG. 3 can obtain a predetermined divided voltage even at the folded portion, and can realize a resistor voltage divider circuit with good linearity accuracy.
第４図は折り返し部の中点から分圧端子を引き
出した本発明の抵抗分圧回路の配置パターン例を
示す図である。各分圧端子A1A間，AC間，CB間
の鋸歯状パターンの繰り返し数は互いに等しく同
図の例では11となつている。第３図の場合と同じ
く直線性のよい分圧電圧が得られる。 FIG. 4 is a diagram showing an example of the layout pattern of the resistive voltage divider circuit of the present invention, in which the voltage divider terminals are drawn out from the midpoint of the folded portion. The number of repetitions of the sawtooth pattern between each voltage dividing terminal A1A , between AC, and between CB is equal to each other and is 11 in the example shown in the figure. As in the case of FIG. 3, a divided voltage with good linearity can be obtained.
第２図〜第４図に示した抵抗分圧回路において
は分圧端子をそれぞれに示す位置から引き出して
いるが、端子間の鋸歯状パターンの繰り返し数が
互いに等しく保たれてさえいれば、分圧端子の引
き出し部の位置はずらすことができる。図示した
引き出し線は簡単のため実線を用いてシンボル化
してある。実際にはメタル配線層等で配置される
が、その形状はMOS集積回路等では特性を左右
することは少ない。MOS集積回路は入力抵抗が
非常に高いため、分圧電圧端子から直流的な定常
電流が出入りする使い方をしなくてすむからであ
る。本発明の抵抗分圧回路は並列形Ａ／Ｄ変換器
に必要となる2M（Ｍビツト）個の基準分圧電圧の
発生回路に適している。設計が容易で直線性にす
ぐれているため、高性能なＡ／Ｄ変換器を実現す
ることが可能となる。 In the resistor voltage divider circuits shown in Figures 2 to 4, the voltage divider terminals are drawn out from the positions shown respectively, but as long as the number of repetitions of the sawtooth pattern between the terminals is kept equal to each other, The position of the lead-out portion of the piezoelectric terminal can be shifted. The illustrated leader lines are symbolized using solid lines for simplicity. In reality, it is arranged in a metal wiring layer, etc., but its shape has little effect on the characteristics of MOS integrated circuits. This is because MOS integrated circuits have extremely high input resistance, so there is no need for them to be used with steady DC current flowing in and out from the divided voltage terminals. The resistive voltage divider circuit of the present invention is suitable for a circuit for generating 2M (M bits) reference divided voltages required for a parallel A/D converter. Since it is easy to design and has excellent linearity, it is possible to realize a high-performance A/D converter.
以上述べたように本発明によれば高精度の抵抗
分圧回路を集積回路化することが容易であり、設
計の手数もかからず、回路調整も不要であるなど
性能の向上や生産における経済性において多大の
効果がある。
As described above, according to the present invention, it is easy to integrate a high-precision resistor voltage divider circuit into an integrated circuit, and there is no need for design work or circuit adjustment, resulting in improved performance and economical production. It has a great effect on sex.
第１図は従来の抵抗分圧回路の構成とパターン
配置例を示す図、第２図〜第４図は本発明の抵抗
分圧回路のパターン配置例を示す図である。
１０……抵抗配線層（ストリツプライン）、１
１……分圧電圧端子、１２……抵抗配線層（櫛形
パターン）、１３……分圧電圧端子、１４……折
り返しパターンの不整合部、１５……折り返しパ
ターンの不整合部、、１６……回路調整パターン、
１７……回路調整パターン。
FIG. 1 is a diagram showing the configuration and pattern arrangement example of a conventional resistive voltage divider circuit, and FIGS. 2 to 4 are diagrams showing pattern layout examples of the resistive voltage divider circuit of the present invention. 10...Resistance wiring layer (stripline), 1
DESCRIPTION OF SYMBOLS 1...Divided voltage terminal, 12...Resistance wiring layer (comb-shaped pattern), 13...Divided voltage terminal, 14...Mismatched portion of folded pattern, 15...Mismatched portion of folded pattern, 16... …Circuit adjustment pattern,
17...Circuit adjustment pattern.
Claims (1)
される抵抗回路であつて、矩形の導体層あるいは
半導体層を互いに直角に複数個、繰り返して配置
し、これらを直列接続することによつて形成した
抵抗回路において、複数個の上記矩形の導体層あ
るいは半導体層から構成される直角の形状の一単
位の抵抗の一辺が、繰り返し配置方向に対し、
45゜の角度で配置されることを特徴とする抵抗回
路。 ２ 前記所定幅をもつ導体層あるいは半導体層で
形成される抵抗回路から分圧電圧を取り出すため
の分圧電圧端子が、前記一単位の抵抗のコーナー
部に配置されたことを特徴とする特許請求の範囲
第１項記載の抵抗回路。[Claims] 1. A resistance circuit formed of conductor layers or semiconductor layers having a predetermined width, in which a plurality of rectangular conductor layers or semiconductor layers are repeatedly arranged at right angles to each other and are connected in series. In the resistor circuit formed by the above method, one side of one unit of a right-angled resistor composed of the plurality of rectangular conductive layers or semiconductor layers is arranged such that one side of the resistor is
A resistor circuit characterized by being arranged at an angle of 45°. 2. A patent claim characterized in that a divided voltage terminal for extracting a divided voltage from a resistor circuit formed of a conductor layer or a semiconductor layer having a predetermined width is arranged at a corner of the one unit of resistor. Range 1. The resistance circuit according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10637084A JPS60250662A (en) | 1984-05-28 | 1984-05-28 | Resistance circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10637084A JPS60250662A (en) | 1984-05-28 | 1984-05-28 | Resistance circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60250662A JPS60250662A (en) | 1985-12-11 |
| JPH0530072B2 true JPH0530072B2 (en) | 1993-05-07 |
Family
ID=14431833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10637084A Granted JPS60250662A (en) | 1984-05-28 | 1984-05-28 | Resistance circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60250662A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7135376B2 (en) | 2003-12-24 | 2006-11-14 | Oki Electric Industry Co., Ltd. | Resistance dividing circuit and manufacturing method thereof |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142667A (en) * | 1986-12-04 | 1988-06-15 | Nec Corp | Gaas semiconductor integrated circuit |
| JPH0341761A (en) * | 1989-07-10 | 1991-02-22 | Nissan Motor Co Ltd | Semiconductor integrated circuit |
| TW330334B (en) * | 1997-08-23 | 1998-04-21 | Winbond Electronics Corp | Static random access memory polysilicon load structure and manufacturing method |
| CN103745974A (en) * | 2014-01-29 | 2014-04-23 | 上海华力微电子有限公司 | Ring resistor structure |
-
1984
- 1984-05-28 JP JP10637084A patent/JPS60250662A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7135376B2 (en) | 2003-12-24 | 2006-11-14 | Oki Electric Industry Co., Ltd. | Resistance dividing circuit and manufacturing method thereof |
| US7456075B2 (en) | 2003-12-24 | 2008-11-25 | Oki Electric Industry Co., Ltd. | Resistance dividing circuit and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60250662A (en) | 1985-12-11 |
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