JP2003234405A - Layout pattern of high precision resistivity - Google Patents
Layout pattern of high precision resistivityInfo
- Publication number
- JP2003234405A JP2003234405A JP2002029346A JP2002029346A JP2003234405A JP 2003234405 A JP2003234405 A JP 2003234405A JP 2002029346 A JP2002029346 A JP 2002029346A JP 2002029346 A JP2002029346 A JP 2002029346A JP 2003234405 A JP2003234405 A JP 2003234405A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- substrate
- resistor
- voltage
- potential difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
【0001】
【発明の属する技術分野】この発明は、半導体ICで
の、複数のP抵抗間の比精度を向上させるためのレイア
ウトパターンに関するものである。
【0002】
【従来の技術】半導体ICにおいてP抵抗を使用し、そ
れらP抵抗の抵抗値の比によって、それらP抵抗の両端に
かかる電圧を分圧した電圧を発生する分圧回路の抵抗部
のレイアウトパターン図を図4に示す。P抵抗素子40
1、402、403、404、405,406が直列に
接続される。全抵抗の両端は端子408、410に接続
され、抵抗素子404と405の中点が端子409に接
続される。
【0003】次に、図4の断面図を図6に示す。P抵抗
素子601、602、603、604、605,606
が直列に接続される。全抵抗の両端は端子608、61
0に接続され、抵抗素子604と605の中点が端子6
09に接続される。
【0004】そのレイアウトパターン図に対応した従来
の回路図を図5に示す。これは、508端子、510端
子にかかる電圧を、509端子、508端子間にある抵
抗値と509端子、510端子間にある抵抗値の比によ
って509端子の電圧が決定される分圧回路である。
【0005】
【発明が解決しようとする課題】半導体ICにおいて、P
抵抗を使用する場合、そのP抵抗の抵抗値を任意に設定
するため、抵抗として使用するポリシリコンの抵抗値
が、設定した抵抗値になるように適度な濃度の不純物を
加える。そのため、そのP抵抗が配置される基盤とP抵抗
の間に電位差が生じた場合、P抵抗内で電子の移動が起
こり見かけ上、P抵抗の不純物濃度が変化する。そのた
めP抵抗と基盤間に電位差が生じた場合、その電位差に
よりP抵抗の抵抗値が変化してしまう。通常半導体ICの
基盤の電位は、そのICで使用する最も高い電位またはも
っとも低い電位が使用されるため、その電圧内で使用さ
れる分圧回路のP抵抗は、電圧の高い側に接続されるP抵
抗と電圧が低い側に接続されるP抵抗の抵抗値のズレ量
が異なる。そのため、同一基板上に配置されたP抵抗を
用いた分圧回路を使用した場合、基盤との電位差の大き
い側のP抵抗と電位差の低い側のP抵抗の抵抗値のズレが
発生してしまう。これは、各抵抗素子がまったく同サイ
ズであり、なおかつ隣接して配置されていたとしても、
各抵抗素子の抵抗値が基盤との電位差によって変化して
しまい、高い比精度を実現できないという問題があっ
た。
【0006】
【課題を解決するための手段】上記課題を解決するため
に、P抵抗を配置する基盤をウェルで分離し、その分離
されたウェルの電位を、そのウェル上に配置するP抵抗
の電位と共通にすることにより、P抵抗と基盤との電位
差を小さくし、電圧の高い側に接続されるP抵抗と電圧
の低い側に接続されるP抵抗の基盤との電位差によって
発生する抵抗値のズレ量を同程度にし、各抵抗素子間の
比精度を向上させる。
【0007】
【発明の実施の形態】上記の様に構成された分圧回路を
用いることにより、P抵抗を配置する基盤をウェルで分
離し、その分離されたウェルの電位を、そのウェル上に
配置するP抵抗の電位と共通にすることにより、P抵抗と
基盤との電位差を小さくし、電圧の高い側に接続される
P抵抗と電圧の低い側に接続されるP抵抗の基盤との電位
差によって発生する抵抗値のズレ量を同程度になるた
め、各抵抗素子間の比精度を向上することが可能とな
る。
【0008】
【実施例】以下にこの発明の実施例を図1に基づいて説
明する。図1は、本発明を含む電圧分圧回路の抵抗部の
パターンレイアウト図である。まず、電圧分圧回路のレ
イアウトレイアウトパターン図を図1に示す。P抵抗素
子101、102、103、104、105,106が
直列に接続される。全抵抗の両端は端子110、112
に接続され、抵抗素子104と105の中点が端子11
1に接続される。その際に、各抵抗が配置される基盤の
電位を各抵抗の中点の電位になるように接続する。各抵
抗の中点に接続された基盤が107,108,109と
なる。
【0009】次に、図1の断面図を図3に示す。P抵抗
素子301、302、303、304、305,306
が直列に接続される。全抵抗の両端は端子310、31
2に接続され、抵抗素子304と305の中点が端子3
11に接続される。また、各抵抗の中点がそれぞれの基
盤307,308,309に接続される。
【0010】そのレイアウトパターン図に対応した回路
図を図2に示す。これは、210端子、212端子にか
かる電圧を、211端子、210端子間にある抵抗値と
211端子、212端子間にある抵抗値の比によって2
11端子の電圧が決定される分圧回路である。
【0011】上記の様に構成された分圧回路を用い、 P
抵抗を配置する基盤をウェルで分離し、その分離された
ウェルの電位を、そのウェル上に配置するP抵抗の電位
と共通にすることにより、P抵抗と基盤との電位差を小
さくし、電圧の高い側に接続されるP抵抗と電圧の低い
側に接続されるP抵抗の基盤との電位差によって発生す
る抵抗値のズレ量を同程度になるため、抵抗値の比精度
を向上することが可能となる。
【0012】
【発明の効果】本発明は、以上説明したように、P抵抗
を配置する基盤をウェルで分離し、その分離されたウェ
ルの電位を、そのウェル上に配置するP抵抗の電位と共
通にすることにより、P抵抗と基盤との電位差を小さく
し、電圧の高い側に接続されるP抵抗と電圧の低い側に
接続されるP抵抗の基盤との電位差によって発生する抵
抗値のズレ量を同程度にし、抵抗値の比精度を向上させ
る効果がある。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout pattern for improving the ratio accuracy between a plurality of P resistors in a semiconductor IC. 2. Description of the Related Art A P-resistor is used in a semiconductor IC, and a resistance of a voltage-dividing circuit for generating a voltage obtained by dividing a voltage applied to both ends of the P-resistor according to a ratio of resistance values of the P-resistors. FIG. 4 shows a layout pattern diagram. P resistance element 40
1, 402, 403, 404, 405, and 406 are connected in series. Both ends of the total resistance are connected to terminals 408 and 410, and the midpoint between the resistance elements 404 and 405 is connected to terminal 409. FIG. 6 is a sectional view of FIG. P resistance elements 601, 602, 603, 604, 605, 606
Are connected in series. Both ends of the total resistance are terminals 608 and 61
0, and the midpoint between the resistance elements 604 and 605 is the terminal 6
09. FIG. 5 shows a conventional circuit diagram corresponding to the layout pattern diagram. This is a voltage divider circuit in which the voltage applied to the 508 and 510 terminals is determined by the ratio of the resistance between the 509 and 508 terminals and the resistance between the 509 and 510 terminals. . [0005] In a semiconductor IC, P
When a resistor is used, in order to arbitrarily set the resistance value of the P resistor, an impurity having an appropriate concentration is added so that the resistance value of polysilicon used as the resistor becomes the set resistance value. Therefore, when a potential difference occurs between the substrate on which the P resistance is disposed and the P resistance, electrons move within the P resistance, and the impurity concentration of the P resistance apparently changes. Therefore, when a potential difference occurs between the P resistance and the substrate, the resistance value of the P resistance changes due to the potential difference. Usually, the highest potential or the lowest potential used in the IC is used as the base potential of the semiconductor IC, so the P resistor of the voltage divider used within that voltage is connected to the higher voltage side The difference between the resistance value of the P resistance and the resistance value of the P resistance connected to the lower voltage side is different. Therefore, when a voltage dividing circuit using P resistors arranged on the same substrate is used, a deviation occurs between the P resistor having a larger potential difference from the substrate and the P resistor having a lower potential difference. . This means that even if each resistor element is exactly the same size and is located adjacent
There is a problem that the resistance value of each resistance element changes due to the potential difference from the substrate, and high specific accuracy cannot be realized. In order to solve the above problems, a substrate on which a P resistor is arranged is separated by a well, and the potential of the separated well is set to the potential of the P resistor arranged on the well. By making it common with the potential, the potential difference between the P resistor and the board is reduced, and the resistance value generated by the potential difference between the P resistor connected to the higher voltage side and the board of the P resistor connected to the lower voltage side Are made substantially the same, and the ratio accuracy between the resistance elements is improved. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS By using a voltage dividing circuit configured as described above, a base on which a P resistor is arranged is separated by a well, and the potential of the separated well is set on the well. The potential difference between the P resistor and the board is reduced by making it common with the potential of the P resistor to be placed, and it is connected to the higher voltage side
Since the amount of deviation of the resistance value caused by the potential difference between the P resistance and the base of the P resistance connected to the lower side of the voltage is substantially the same, it is possible to improve the relative accuracy between the respective resistance elements. An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a pattern layout diagram of a resistor section of a voltage dividing circuit including the present invention. First, FIG. 1 shows a layout pattern diagram of the voltage dividing circuit. P resistance elements 101, 102, 103, 104, 105, and 106 are connected in series. Both ends of the total resistance are terminals 110 and 112
And the middle point between the resistance elements 104 and 105 is the terminal 11
Connected to 1. At this time, connection is made so that the potential of the substrate on which the resistors are arranged is the potential of the middle point of each resistor. The bases connected to the midpoints of the resistors are 107, 108, and 109. Next, FIG. 3 shows a sectional view of FIG. P resistance elements 301, 302, 303, 304, 305, 306
Are connected in series. Both ends of the total resistance are terminals 310 and 31
2 and the middle point between the resistance elements 304 and 305 is the terminal 3
11 is connected. The midpoint of each resistor is connected to each of the bases 307, 308, 309. FIG. 2 shows a circuit diagram corresponding to the layout pattern diagram. This is because the voltage applied to the terminals 210 and 212 is determined by the ratio of the resistance between the terminals 211 and 210 to the resistance between the terminals 211 and 212.
This is a voltage dividing circuit for determining the voltage of the 11 terminals. Using the voltage dividing circuit constructed as described above,
The substrate on which the resistor is placed is separated by a well, and the potential of the separated well is made common to the potential of the P resistor placed on the well, thereby reducing the potential difference between the P resistor and the substrate, Since the amount of deviation of the resistance value caused by the potential difference between the P resistance connected to the high side and the base of the P resistance connected to the low side is almost the same, it is possible to improve the accuracy of the resistance ratio It becomes. As described above, according to the present invention, the base on which the P resistance is disposed is separated by a well, and the potential of the separated well is made equal to the potential of the P resistance disposed on the well. By making them common, the potential difference between the P resistance and the substrate is reduced, and the deviation in the resistance value caused by the potential difference between the P resistance connected to the higher voltage side and the P resistance substrate connected to the lower voltage side. This has the effect of making the amounts the same and improving the accuracy of the resistance value ratio.
【図面の簡単な説明】
【図1】本発明の抵抗素子のレイアウトパターンであ
る。
【図2】抵抗素子を使用する回路図である。
【図3】抵抗素子を使用するレイアウト断面図である。
【図4】従来の抵抗素子のレイアウトパターンである。
【図5】従来の抵抗素子を使用する回路図である。
【図6】従来の抵抗素子を使用するレイアウト断面図で
ある。
【符号の説明】
101、102、103、104、105,106 抵
抗素子パターン
107、108、109 抵抗素子を配置する電気的に
分離された基盤
110、112 電圧入力端子
111 電圧出力端子
201、202、203、204、205,206 抵
抗素子
207、208、209 抵抗素子を配置する電気的に
分離された基盤
210、212 電圧入力端子
211 電圧出力端子
301、302、303、304、305,306 抵
抗素子パターン
307、308、309 抵抗素子を配置する電気的に
分離された基盤
310、312 電圧入力端子
311 電圧出力端子
401、402、403、404、405,406 抵
抗素子パターン
407 抵抗素子を配置する基盤
408、410 電圧入力端子
409 電圧出力端子
501、502、503、504、505,506 抵
抗素子
507 抵抗素子を配置する基盤
508、510 電圧入力端子
509 電圧出力端子
601、602、603、604、605,606 抵
抗素子パターン
607 抵抗素子を配置する基盤
608、610 電圧入力端子
609 電圧出力端子BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout pattern of a resistance element according to the present invention. FIG. 2 is a circuit diagram using a resistance element. FIG. 3 is a layout sectional view using a resistance element. FIG. 4 is a layout pattern of a conventional resistance element. FIG. 5 is a circuit diagram using a conventional resistance element. FIG. 6 is a layout cross-sectional view using a conventional resistance element. DESCRIPTION OF SYMBOLS 101, 102, 103, 104, 105, 106 Resistive element patterns 107, 108, 109 Electrically separated bases 110, 112 on which resistive elements are arranged Voltage input terminals 111 Voltage output terminals 201, 202, 203, 204, 205, 206 Resistance elements 207, 208, 209 Electrically separated bases 210, 212 on which resistance elements are arranged Voltage input terminal 211 Voltage output terminals 301, 302, 303, 304, 305, 306 Resistance element pattern 307, 308, 309 Electrically separated bases 310, 312 on which resistive elements are arranged Voltage input terminals 311 Voltage output terminals 401, 402, 403, 404, 405, 406 Resistive element patterns 407 Bases 408 on which resistive elements are arranged 410 Voltage input terminal 409 Voltage output terminal 501, 5 2, 503, 504, 505, 506 Resistance element 507 Base 508, 510 on which resistance element is disposed Voltage input terminal 509 Voltage output terminal 601, 602, 603, 604, 605, 606 Resistance element pattern 607 Base 608 on which resistance element is disposed , 610 voltage input terminal 609 voltage output terminal
Claims (1)
(以下P抵抗とする)のレイアウトパターンにおいて、 そのP抵抗がおかれる基盤の電位を分割し、P抵抗と基
盤間の電位差を低減させることを特徴とするICレイア
ウトパターン。Claims: 1. A polysilicon resistor element for a semiconductor integrated circuit.
An IC layout pattern, wherein a potential of a substrate on which the P resistance is placed is divided to reduce a potential difference between the P resistance and the substrate in a layout pattern (hereinafter referred to as a P resistance).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002029346A JP2003234405A (en) | 2002-02-06 | 2002-02-06 | Layout pattern of high precision resistivity |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002029346A JP2003234405A (en) | 2002-02-06 | 2002-02-06 | Layout pattern of high precision resistivity |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003234405A true JP2003234405A (en) | 2003-08-22 |
Family
ID=27773650
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002029346A Withdrawn JP2003234405A (en) | 2002-02-06 | 2002-02-06 | Layout pattern of high precision resistivity |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2003234405A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007036124A (en) * | 2005-07-29 | 2007-02-08 | Seiko Instruments Inc | Semiconductor device |
JP2010109233A (en) * | 2008-10-31 | 2010-05-13 | Renesas Technology Corp | Semiconductor device |
JP2014041882A (en) * | 2012-08-21 | 2014-03-06 | Lapis Semiconductor Co Ltd | Resistance structure, integrated circuit, and manufacturing method of resistance structure |
JP2014099639A (en) * | 2014-01-15 | 2014-05-29 | Renesas Electronics Corp | Semiconductor device |
JP2015115352A (en) * | 2013-12-09 | 2015-06-22 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor device |
JP2017123481A (en) * | 2017-03-09 | 2017-07-13 | ラピスセミコンダクタ株式会社 | Semiconductor device |
-
2002
- 2002-02-06 JP JP2002029346A patent/JP2003234405A/en not_active Withdrawn
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007036124A (en) * | 2005-07-29 | 2007-02-08 | Seiko Instruments Inc | Semiconductor device |
JP2010109233A (en) * | 2008-10-31 | 2010-05-13 | Renesas Technology Corp | Semiconductor device |
JP2014041882A (en) * | 2012-08-21 | 2014-03-06 | Lapis Semiconductor Co Ltd | Resistance structure, integrated circuit, and manufacturing method of resistance structure |
JP2015115352A (en) * | 2013-12-09 | 2015-06-22 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor device |
JP2014099639A (en) * | 2014-01-15 | 2014-05-29 | Renesas Electronics Corp | Semiconductor device |
JP2017123481A (en) * | 2017-03-09 | 2017-07-13 | ラピスセミコンダクタ株式会社 | Semiconductor device |
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