JP2531628B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2531628B2 JP2531628B2 JP61106746A JP10674686A JP2531628B2 JP 2531628 B2 JP2531628 B2 JP 2531628B2 JP 61106746 A JP61106746 A JP 61106746A JP 10674686 A JP10674686 A JP 10674686A JP 2531628 B2 JP2531628 B2 JP 2531628B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- internal load
- semiconductor device
- power supply
- hole portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマスタスライス方式の半導体装置に適用して
好適な半導体装置関し、特に内部負荷回路への供給電圧
の調整を容易にした半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for application to a master slice type semiconductor device, and more particularly to a semiconductor device that facilitates adjustment of a supply voltage to an internal load circuit. .
従来、マスタスライス方式を始めとする一の種類の半
導体装置では、複数の内部負荷回路に夫々外部最低電源
電圧を供給させる構成を採っているが、この外部最低電
源電圧端子から各内部負荷回路に到る配線経路の相違か
ら、夫々の配線における電位に変動が生じることがあ
る。このため、各内部負荷回路における電気的特性に期
待したものが得られず、半導体装置の特性の劣化を招く
ことがある。Conventionally, one type of semiconductor device, such as the master slice method, has adopted a configuration in which a plurality of internal load circuits are respectively supplied with an external minimum power supply voltage, but from this external minimum power supply voltage terminal to each internal load circuit. Due to the difference in the reaching wiring path, the potential in each wiring may vary. For this reason, the expected electrical characteristics of each internal load circuit cannot be obtained, and the characteristics of the semiconductor device may be deteriorated.
このため、従来では夫々の内部負荷回路内の素子形状
や寸法等を変更して抵抗値，トランジスタ形状，或いは
容量値等を調整し、外部最低電源電圧の変動に対する補
償を行っている。Therefore, conventionally, the resistance value, the transistor shape, the capacitance value, or the like is adjusted by changing the element shape, size, or the like in each internal load circuit to compensate for the fluctuation of the external minimum power supply voltage.
上述した従来の半導体装置は、素子形状や寸法等を最
初から設計する半導体装置においては有効であるが、マ
スタスライス方式の半導体装置のように、既に形成され
ている素子に対して配線構造のみを変更して所要の機能
の装置を構成する半導体装置には適用することかでき
ず、半導体装置の特性を向上する上での障害になってい
る。The conventional semiconductor device described above is effective in a semiconductor device in which the element shape, dimensions, etc. are designed from the beginning, but only a wiring structure is provided for already formed elements like a master slice type semiconductor device. It cannot be applied to a semiconductor device that is modified to form a device having a required function, which is an obstacle to improving the characteristics of the semiconductor device.
本発明の半導体装置は、マスタスライス方式の半導体
装置においても各内部負荷回路に夫々好適な外部最低電
源電圧を調節して供給することを可能とするものであ
る。The semiconductor device of the present invention can adjust and supply a suitable external minimum power supply voltage to each internal load circuit even in a master slice type semiconductor device.
本発明の半導体装置は、夫々異なる内部負荷回路に接
続された複数本の第１の導電層と、これら第１の導電層
に交差して所定の電源電圧端子に接続されている第２の
導電層と、前記各第１の導電層と第２の導電層とを夫々
個別に電気接続する複数個のスルーホール部とを備え、
前記各第１の導電層に対する夫々のスルーホール部の位
置を前記第２の導電層の幅方向に相違させ、かつ電源電
圧端子に対して第２の導電層の長さ方向に遠い位置のス
ルーホール部を、これよりも近い位置のスルーホール部
よりも内部負荷回路に近い幅方向の位置に設定し、これ
により遠い位置のスルーホール部に接続される第１の導
電層の配線抵抗を、これよりも近い位置のスルーホール
部に接続される第１の導電層の配線抵抗よりも小さくし
た構成としている。A semiconductor device according to the present invention includes a plurality of first conductive layers connected to different internal load circuits, and a second conductive layer that intersects the first conductive layers and is connected to a predetermined power supply voltage terminal. A layer, and a plurality of through-hole portions for individually electrically connecting the first conductive layer and the second conductive layer, respectively,
The positions of the respective through holes with respect to each of the first conductive layers are made different in the width direction of the second conductive layer, and the through holes at positions far from the power supply voltage terminal in the length direction of the second conductive layer are formed. The hole portion is set at a position in the width direction closer to the internal load circuit than the through hole portion located closer to the hole portion, and the wiring resistance of the first conductive layer connected to the through hole portion located farther is thereby set, The wiring resistance of the first conductive layer connected to the through hole portion closer than this is smaller than the wiring resistance.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のレイアウト図、第２図は
その要部の拡大図であり、ここではマスタスライス方式
の半導体装置に本発明を適用した例を示している。FIG. 1 is a layout diagram of an embodiment of the present invention, and FIG. 2 is an enlarged view of a main part thereof. Here, an example in which the present invention is applied to a master slice type semiconductor device is shown.
これらの図において、１は既に所定の素子形状，寸法
に形成された内部負荷回路としての内部セル列であり、
複数子のセルを配列している。また、２及び３はこれら
内部負荷回路１に夫々最低，最高の電源電圧を供給する
ための外部最低電源電圧端子及び外部最高電源電圧端子
であり、４は各種の信号端子である。これらはチップの
周辺に沿って配列している。In these figures, 1 is an internal cell row as an internal load circuit already formed in a predetermined element shape and size,
Multiple child cells are arranged. Further, 2 and 3 are external minimum power supply voltage terminals and external maximum power supply voltage terminals for supplying the minimum and maximum power supply voltages to the internal load circuit 1, respectively, and 4 is various signal terminals. These are arranged along the periphery of the chip.
そして、前記内部負荷回路１は下層の内部配線5a〜5i
によって所要の機能を有する複数個の内部負荷回路1a〜
1iとして構成しており、しかも夫々の負荷回路には前記
下層の配線の一部を用いて構成した第１の導電層7a〜7i
に夫々スルーホール6a〜6iを介して接続している。これ
ら第１の導電層7a〜7iは夫々Ｙ方向（図の上下方向）に
沿って平行に延設しており、夫々の端部は前記外部最低
電源電圧端子２の近傍位置まで延設している。Then, the internal load circuit 1 includes the internal wirings 5a to 5i in the lower layer.
Depending on the number of internal load circuits 1a
1i, and the first conductive layers 7a to 7i are configured by using a part of the lower wiring for each load circuit.
To the respective through holes 6a to 6i. The first conductive layers 7a to 7i extend in parallel along the Y direction (vertical direction in the drawing), and their ends extend to positions near the external lowest power supply voltage terminal 2. There is.
一方、前記外部最低電源電圧端子２の隣接位置には上
層配線の一部を用いて前記各１の導電層7a〜7iと略直角
に交差する最低電圧配線として第２の導電層８を延設
し、これを前記外部最低電源電圧端子２に直接接続して
いる。この第２の導電層８の下層位置でしかも前記外部
最低電源電圧端子２の近傍位置には前記内部負荷回路１
で使用される最低電源電圧によって決められる内部負荷
回路用の定電圧発生回路９を形成している。また、前記
上層配線の他部は内部負荷回路１に接続する最高電圧配
線10として構成し、これを前記外部最高電源電圧端子３
に直接接続して前記内部負荷回路１に適宜接続した構成
としている。On the other hand, at a position adjacent to the external lowest power supply voltage terminal 2, a second conductive layer 8 is extended by using a part of the upper layer wiring as a lowest voltage wiring intersecting each of the one conductive layers 7a to 7i at a substantially right angle. However, this is directly connected to the external lowest power supply voltage terminal 2. The internal load circuit 1 is provided at a position below the second conductive layer 8 and near the external lowest power supply voltage terminal 2.
Forming a constant voltage generating circuit 9 for an internal load circuit which is determined by the lowest power supply voltage used in. The other part of the upper layer wiring is configured as the highest voltage wiring 10 connected to the internal load circuit 1, and this is formed as the highest voltage terminal 3
Is directly connected to the internal load circuit 1.
しかる上で、前記第２の導電層８を、前記定電圧発生
回路９及び中央の内部負荷回路1aに対して配置された第
１の導電層7aの夫々にスルーホール11aを介して接続
し、発生された定電圧を第２の導電層８を介して第１の
導電層7a、即ち内部負荷回路1aに供給している。この場
合、内部負荷回路1aにおける最低電圧はスルーホール11
aの配設点によって決定される。Then, the second conductive layer 8 is connected to each of the constant voltage generating circuit 9 and the first conductive layer 7a arranged with respect to the central internal load circuit 1a through through holes 11a. The generated constant voltage is supplied to the first conductive layer 7a, that is, the internal load circuit 1a via the second conductive layer 8. In this case, the minimum voltage in the internal load circuit 1a is the through hole 11
Determined by the placement point of a.
また、他の内部負荷回路1b〜1iは、夫々第１の導電層
7b〜7iと第２の導電層８の交差部に夫々設けたスルーホ
ール11b〜11iによって電気的接続を行い、各内部負荷回
路1b〜1iに定電圧発生回路９の最低電圧を供給している
が、このとき、各スルーホール11b〜11iの第２の導電層
８の幅方向における位置を夫々変化させている。即ち、
この図示の例では中央の内部負荷回路1aの両側の内部負
荷回路1b,1fから順次外側の内部負荷回路に向かってス
ルーホールの幅方向位置を内部負荷回路に徐々に近くな
るような位置に配設している。つまり、ここではスルー
ホール11aが内部負荷回路からの距離が最も大きい位置
にあり、スルーホール11b,11c,11d,11e及びスルーホー
ル11f,11g,11h,11iの順で内部回路からの距離が短くな
るようにしている。Further, the other internal load circuits 1b to 1i are respectively connected to the first conductive layer.
Electrical connection is made by through holes 11b to 11i provided at the intersections of 7b to 7i and the second conductive layer 8, respectively, and the minimum voltage of the constant voltage generating circuit 9 is supplied to each of the internal load circuits 1b to 1i. However, at this time, the positions of the through holes 11b to 11i in the width direction of the second conductive layer 8 are changed. That is,
In this illustrated example, the through holes are arranged such that the positions in the width direction of the through holes gradually become closer to the internal load circuit from the internal load circuits 1b and 1f on both sides of the central internal load circuit 1a toward the outer internal load circuits. I have set up. That is, here, the through hole 11a is located at the position where the distance from the internal load circuit is the largest, and the distance from the internal circuit is short in the order of the through holes 11b, 11c, 11d, 11e and the through holes 11f, 11g, 11h, 11i. I am trying to become.
この構成によれば、各内部負荷回路から各スルーホー
ルに到る各第１の導電層7b〜7iの実質的な配線長は中央
位置の第１の導電層7aに比較して両側に位置するものほ
ど短い状態にされるので、配線抵抗等がそれだけ低減さ
れることになる。このため、第２の導電層８の長さ方向
における各スルーホール11b〜11iの配設位置の相違によ
る抵抗の相違をこの第１の導電層における配線抵抗の低
減分で補正でき、結果的に全ての内部負荷回路に達する
までの配線抵抗を均一化できる。このため、定電圧発生
回路９から各内部負荷回路1a〜1iに供給される最低電圧
の変動を防止でき、電気的特性に優れた半導体装置を構
成できる。According to this structure, the substantial wiring lengths of the first conductive layers 7b to 7i from the internal load circuits to the through holes are located on both sides as compared with the first conductive layer 7a at the central position. Since the shorter the length, the shorter the wiring resistance and the like. Therefore, the difference in resistance due to the difference in the arrangement position of the through holes 11b to 11i in the length direction of the second conductive layer 8 can be corrected by the reduction of the wiring resistance in the first conductive layer, and as a result, It is possible to equalize the wiring resistance until reaching all the internal load circuits. Therefore, it is possible to prevent the fluctuation of the minimum voltage supplied from the constant voltage generation circuit 9 to each of the internal load circuits 1a to 1i, and to configure a semiconductor device having excellent electrical characteristics.
したがって、マスタースライス方式の半導体装置にお
いても単にスルーホールの配設位置を変化調整するだけ
で各内部負荷回路に均一な最低電圧を供給でき、設計及
び製造の容易化，迅速化を達成できる。Therefore, even in the master slice type semiconductor device, a uniform minimum voltage can be supplied to each internal load circuit by simply adjusting the position of the through hole, and the design and manufacturing can be facilitated and speeded up.
ここで、各スルーホールの配設位置は第1,第２の各導
電層の幅，長さによって適宜変化調節することは言うま
でもない。Here, it goes without saying that the positions where the respective through holes are provided are appropriately changed and adjusted depending on the widths and lengths of the first and second conductive layers.
以上説明したように本発明は、夫々異なる内部負荷回
路に接続された複数本の第１の導電層と、これら第１の
導電層と略直角に交差して外部最低電源電圧端子に接続
された第２の導電層とを夫々個別に電気接続する複数庫
のスルーホール部の位置を第２の導電層の幅方向に相違
させ、かつ電源電圧端子に対して第２の導電層の長さ方
向に遠い位置のスルーホール部を、これよりも近い位置
のスルーホール部よりも内部負荷回路に近い幅方向の位
置に設定し、これにより遠い位置のスルーホール部に接
続される第１の導電層の配線抵抗を、これよりも近い位
置のスルーホールに接続される第１の導電層の配線抵抗
よりも小さくているので、マスタスライス方式の半導体
装置においても配線パターンの設計を変更調節するだけ
で各内部負荷回路に夫々均一な電圧を供給でき、これに
より電気的特性の改善及び製造歩留の向上を達成でき
る。As described above, according to the present invention, a plurality of first conductive layers respectively connected to different internal load circuits and a plurality of first conductive layers intersecting the first conductive layers at substantially right angles are connected to the external lowest power supply voltage terminal. The positions of the through-holes of the plurality of compartments that are electrically connected to the second conductive layer individually are different from each other in the width direction of the second conductive layer, and in the length direction of the second conductive layer with respect to the power supply voltage terminal. The first conductive layer connected to the through-hole portion at a position farther from the through-hole portion is set at a position in the width direction closer to the internal load circuit than the through-hole portion at a position closer thereto. Has a wiring resistance smaller than the wiring resistance of the first conductive layer connected to the through hole located closer than this, it is only necessary to change and adjust the design of the wiring pattern even in the master slice type semiconductor device. For each internal load circuit S can supply uniform voltage, thereby achieving improved and increased the production yield of the electrical characteristics.
第１図は本発明の一実施例の一部のレイアウト図、第２
図は要部の拡大図である。 1,1a〜1i……内部負荷回路、２……外部最低電源電圧端
子、３……外部最高電源電圧端子、４……信号端子、5a
〜5i……内部配線、6a〜6i……スルーホール、7a〜7i…
…第１の導電層、８……第２の導電層、９……定電圧発
生回路、10……最高電圧配線、11a〜11i……スルーホー
ル。FIG. 1 is a partial layout diagram of an embodiment of the present invention, and FIG.
The figure is an enlarged view of the main part. 1,1a-1i …… Internal load circuit, 2 …… External lowest power supply voltage terminal, 3 …… External highest power supply voltage terminal, 4 …… Signal terminal, 5a
~ 5i …… Internal wiring, 6a ～ 6i …… Through hole, 7a ～ 7i…
... first conductive layer, 8 ... second conductive layer, 9 ... constant voltage generating circuit, 10 ... highest voltage wiring, 11a to 11i ... through holes.
Claims (1)
本の平行な第１の導電層と、これら第１の導電層に交差
して所定の電源電圧端子に接続されている第２の導電層
と、前記各第１の導電層と第２の導電層とを夫々個別に
電気接続する複数個のスルーホール部とを備え、前記各
第１の導電層に対する夫々のスルーホール部の位置を前
記第２の導電層の幅方向に相違させており、かつ前記電
源電圧端子に対して第２の導電層の長さ方向に遠い位置
のスルーホール部を、これよりも近い位置のスルーホー
ル部よりも内部負荷回路に近い幅方向の位置に設定し、
前記遠い位置のスルーホール部に接続される第１の導電
層の配線抵抗を、これよりも近い位置のスルーホール部
に接続される第１の導電層の配線抵抗よりも小さくした
ことを特徴とする半導体装置。1. A plurality of parallel first conductive layers connected to different internal load circuits, respectively, and a second conductive layer intersecting the first conductive layers and connected to a predetermined power supply voltage terminal. A plurality of through holes for electrically connecting the first conductive layer and the second conductive layer to each other, and the position of each through hole with respect to each of the first conductive layers. A through hole portion which is different in the width direction of the second conductive layer and is far from the power supply voltage terminal in the length direction of the second conductive layer is a through hole portion closer to the through hole portion. Set to a position in the width direction closer to the internal load circuit,
The wiring resistance of the first conductive layer connected to the through hole portion at the distant position is made smaller than the wiring resistance of the first conductive layer connected to the through hole portion at a position closer than this. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61106746A JP2531628B2 (en) | 1986-05-12 | 1986-05-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61106746A JP2531628B2 (en) | 1986-05-12 | 1986-05-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62263654A JPS62263654A (en) | 1987-11-16 |
| JP2531628B2 true JP2531628B2 (en) | 1996-09-04 |
Family
ID=14441483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61106746A Expired - Fee Related JP2531628B2 (en) | 1986-05-12 | 1986-05-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2531628B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58124262A (en) * | 1982-01-20 | 1983-07-23 | Nec Corp | Integrated circuit device |
| JPS58166743A (en) * | 1982-03-29 | 1983-10-01 | Nec Corp | Master-slice substrate |
-
1986
- 1986-05-12 JP JP61106746A patent/JP2531628B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62263654A (en) | 1987-11-16 |
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