JPH0760823B2 - Semiconductor integrated device - Google Patents
Semiconductor integrated deviceInfo
- Publication number
- JPH0760823B2 JPH0760823B2 JP61132530A JP13253086A JPH0760823B2 JP H0760823 B2 JPH0760823 B2 JP H0760823B2 JP 61132530 A JP61132530 A JP 61132530A JP 13253086 A JP13253086 A JP 13253086A JP H0760823 B2 JPH0760823 B2 JP H0760823B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- extension
- wiring
- layer
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積装置、特に高分解能の並列比較形AD
変換器を構成する半導体集積装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a semiconductor integrated device, particularly a high-resolution parallel comparison type AD.
The present invention relates to a semiconductor integrated device that constitutes a converter.
従来、並列比較形のAD変換器を半導体集積装置で構成す
る場合、半導体基板上に複数の比較器を並べ、それぞれ
の比較器に基準電圧を与えるために、これらの比較器の
列と平行して一定幅の配線パターンを設け、この配線パ
ターンの一定区間長を基準抵抗に流用し、このパターン
の一定区間長ごとにそれぞれの比較器との接続配線パタ
ーンを設けた構成にしている。ところで、この変換器は
分解能をｎビットとすると、2n−１個の比較器と2n個の
基準抵抗を必要とするので、高分解能の変換器では総て
の比較器と基準抵抗用の配線パターンとを一直線に配置
することが困難となり、適当個数の比較器ごとに折返し
た形をとっている。また、この折返した形の配置では、
それぞれの比較器の出力をできるだけ遅延時間を少なく
してエンコーダ部に与えるため、比較器の列間にエンコ
ーダ部を配置し、基準抵抗用の配線パターンは２列に並
んだ比較器の列の外側に設けられている。このため、こ
の２列の配線パターンを結ぶ折返し部の配線パターンの
長さが非常に長くなり、この部分の抵抗値を基準抵抗値
と等しくするために、上記の一定幅の配線パターンより
遥かに広い配線パターンで接続するとか、製造上の抵抗
値偏差を等しくするために、多数の上記の一定幅の配線
パターンを並列に設けて接続している。Conventionally, when a parallel comparison type AD converter is configured by a semiconductor integrated device, a plurality of comparators are arranged on a semiconductor substrate, and in order to give a reference voltage to each comparator, the comparators are arranged in parallel with each other. A wiring pattern having a certain width is provided, a certain section length of this wiring pattern is used as a reference resistance, and a connection wiring pattern with each comparator is provided for each certain section length of this pattern. By the way, this converter requires 2 n -1 comparators and 2 n reference resistors, assuming that the resolution is n bits, so in a high-resolution converter, all comparators and reference resistors are used. It is difficult to arrange the wiring pattern and the wiring pattern in a straight line, and the wiring pattern is formed by folding back an appropriate number of comparators. Also, in this folded configuration,
Since the output of each comparator is given to the encoder part with the minimum delay time, the encoder part is arranged between the comparator lines and the wiring pattern for the reference resistor is located outside the two comparator lines. It is provided in. For this reason, the length of the wiring pattern of the folded portion connecting the two rows of wiring patterns becomes very long, and in order to make the resistance value of this portion equal to the reference resistance value, it is far more than the above-mentioned wiring pattern of a constant width. In order to connect with a wide wiring pattern or to equalize the resistance deviation in manufacturing, a large number of wiring patterns having the above-mentioned constant width are provided in parallel and connected.
しかしながら、上述の従来のAD変換器の半導体集積装置
は、折返し部の抵抗が比較器と平行した一定幅の配線パ
ターンの延長部の抵抗と、この延長部間を接続する配線
パターン接続部の抵抗とからなるため、折返し部の抵抗
を基準抵抗と等しくするには、配線パターン接続部の幅
を極めて広くしなければならないとか、上記の一定幅の
配線パターンにより接続するものでは、並列本数を増す
だけ延長部も長くなり、その部分の抵抗が加わって単に
並列本数を増した分だけ抵抗値が下らず、基板上に広い
面積を占有することになって、その分、集積度が向上し
ないと云う問題点を有している。However, in the semiconductor integrated device of the conventional AD converter described above, the resistance of the folded portion is the resistance of the extension portion of the wiring pattern having a constant width in parallel with the comparator and the resistance of the wiring pattern connection portion that connects the extension portions. Therefore, in order to make the resistance of the folded portion equal to the reference resistance, the width of the wiring pattern connecting portion must be extremely wide, or the number of parallel lines is increased in the case of connecting with the wiring pattern of the above constant width. The extension also becomes longer, and the resistance value does not decrease as much as the number of parallel lines is increased by adding the resistance of that part, occupying a large area on the substrate, and the degree of integration does not improve accordingly. There is a problem called.
本発明の目的は上述した問題点を除去し、折返し部の面
積を小さくすることにより、集積度の向上した並列比較
形AD変換器を構成した半導体集積装置を提供することに
ある。An object of the present invention is to eliminate the above-mentioned problems and to provide a semiconductor integrated device in which a parallel comparison type AD converter having an improved degree of integration is configured by reducing the area of a folded portion.
本発明は基準抵抗に流用する一定幅の直線状配線パター
ンと、この配線パターンに並んで設けられた多数の比較
器とを組として、この組を複数並べて１つのAD変換器を
構成する半導体集積装置において、隣接する上記配線パ
ターンのそれぞれの端部を接続する配線パターン延長部
の配線パターンをそれぞれスルーホールにより接続され
た多層構造により構成される。The present invention relates to a semiconductor integrated circuit in which a linear wiring pattern having a constant width, which is diverted to a reference resistor, and a large number of comparators arranged side by side in the wiring pattern are set as a set, and a plurality of the sets are arranged to form one AD converter. In the device, the wiring pattern of the wiring pattern extension connecting the respective ends of the adjacent wiring patterns is connected by through holes to form a multilayer structure.
また、配線パターン延長部の第１層目の配線パターン幅
が上記の一定幅で、スルーホールにより接続された多層
目の配線パターン延長部の幅が上記一定幅より広くして
構成される。Further, the wiring pattern width of the first layer of the wiring pattern extension is the above-mentioned constant width, and the width of the wiring pattern extension of the multilayer connected by the through hole is wider than the above-mentioned constant width.
以下、本発明の実施例について図面を参照して説明す
る。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）は本発明の一実施例の平面図で、配線パタ
ーン延長部が２層構造で構成された場合を示している。
図において、シリコン基板１の上にエンコーダ部２を挟
んで、２列に複数の比較器３が設けられていて、これら
の比較器３に沿ってそれぞれエンコーダ部と反対側に一
定幅の例えばアルミニュームの配線パターン４が設けら
れている。この配線パターン４の一定長は基準抵抗とし
て用いられて、基準電圧をそれぞれの比較器３に与える
ために、このパターン４の一定長ごとにそれぞれの比較
器３との接続用の配線パターンを有している。また配線
パターン４はそれぞれの比較器３の列をはずれた部分に
配線パターン延長部５を有していて、配線パターン４と
ほぼ同じ幅を有する複数の配線パターンからなる配線パ
ターン接続部７が配線パターン延長部５の間を接続して
基準抵抗を形成している。さらに配線パターン延長部５
は２層構造になっていて、配線パターン延長部５の第１
層目延長部5Aと第２層目延長部5Bとはスルーホール６に
より接続されている。FIG. 1 (a) is a plan view of an embodiment of the present invention, and shows a case where the wiring pattern extension has a two-layer structure.
In the figure, a plurality of comparators 3 are provided in two rows on a silicon substrate 1 with an encoder section 2 sandwiched between them. The wiring pattern 4 of the num is provided. The fixed length of the wiring pattern 4 is used as a reference resistance, and in order to apply a reference voltage to each comparator 3, a wiring pattern for connection with each comparator 3 is provided for each fixed length of the pattern 4. is doing. In addition, the wiring pattern 4 has a wiring pattern extension 5 at a portion out of the row of the respective comparators 3, and a wiring pattern connecting portion 7 composed of a plurality of wiring patterns having substantially the same width as the wiring pattern 4 is wired. The pattern extension portions 5 are connected to form a reference resistance. Furthermore, the wiring pattern extension 5
Has a two-layer structure, and the first part of the wiring pattern extension 5 is
The through hole 6 connects the layer extension 5A and the second layer extension 5B.
第１図（ｂ）は第１図（ａ）におけるＹ−Ｙ′線の断面
図で、シリコン基板１の上に二酸化シリコン絶縁層８が
設けられ、この絶縁層の上に配線パターン４、配線ポタ
ーン延長部５の第１層目延長部5Aおよび配線パターン接
続部７が設けられて、これらの上にCVD法等によって作
られた絶縁層９を介して第２層目延長部5Bが設けられ、
この第１層目延長部5Aと第２層目延長部5Bとがスルーホ
ール６により接続されていることを示している。FIG. 1 (b) is a cross-sectional view taken along the line YY 'in FIG. 1 (a). A silicon dioxide insulating layer 8 is provided on a silicon substrate 1, and a wiring pattern 4 and wiring are provided on this insulating layer. The first layer extension 5A of the pattern extension 5 and the wiring pattern connection portion 7 are provided, and the second layer extension 5B is provided on the first layer extension 5A and the wiring pattern connection portion 7 via the insulating layer 9 formed by the CVD method or the like. ,
It is shown that the first layer extension 5A and the second layer extension 5B are connected by the through hole 6.
なお、以上の実施例では配線パターン延長部を２層構造
としたが、さらに多層構造としてこれらの延長部を総て
スルーホールにより接続してもよい。In the above embodiments, the wiring pattern extension has a two-layer structure, but a multilayer structure may be used to connect all the extension with through holes.
また以上の実施例では配線パターンをアルミニュームと
したが、他の導電材により作られても一向に拘はない。Further, although the wiring pattern is made of aluminum in the above embodiments, it may be made of other conductive material.
以上詳細に説明したとおり、本発明は折返し部の配線パ
ターン延長部を多層構造とすることと、２層目を含む上
層の延長部のパターン幅を広くして一層目の延長部とス
ルーホール接続することにより、一層目の配線層と二層
目を含む上層の配線層とが並列に接続されて、配線パタ
ーン延長部の等価抵抗を著しく減少することができて、
延長部間を接続する配線パターン接続部の並列配線パタ
ーンの本数が少なくて済み、折返し部の面積を小さくで
きる。また配線パターン延長部の抵抗を著しく減少させ
ることにより、製造工程において配線パターン幅の仕上
り寸法に一様に偏差があっても、直線状の配線パターン
による基準抵抗と、折返し部の配線パターン接続部の抵
抗とは相対比を合わせることができる。それは配線パタ
ーン接続部の抵抗は直線状の配線パターンを複数並列接
続された構成となっているので製造誤差が等価となるた
めで、その結果精度の高いAD変換器を実現できると云う
効果がある。As described above in detail, according to the present invention, the wiring pattern extension of the folded portion has a multilayer structure, and the pattern width of the extension of the upper layer including the second layer is widened to connect the extension of the first layer to the through hole. By doing so, the wiring layer of the first layer and the wiring layer of the upper layer including the second layer are connected in parallel, and the equivalent resistance of the wiring pattern extension can be significantly reduced,
The number of parallel wiring patterns of the wiring pattern connecting portion connecting the extension portions can be small, and the area of the folded portion can be reduced. In addition, by significantly reducing the resistance of the wiring pattern extension, even if there is a uniform deviation in the finished dimensions of the wiring pattern width during the manufacturing process, the reference resistance due to the linear wiring pattern and the wiring pattern connection at the folded portion The relative ratio can be matched with the resistance of. This is because the resistance of the wiring pattern connection part is configured by connecting a plurality of linear wiring patterns in parallel, so that manufacturing errors are equivalent, and as a result, it is possible to realize a highly accurate AD converter. .
なおまた、配線パターン接続部を単独の広い配線パター
ンで構成した場合も、配線パターン延長部を多層構造と
することにより、この延長部の抵抗を著しく低くできる
ので、折返し部の抵抗をほぼこの接続部のパターン幅か
ら基準抵抗に設定できると云う効果がある。Even when the wiring pattern connecting portion is composed of a single wide wiring pattern, the resistance of the wiring pattern extending portion can be remarkably reduced by forming the wiring pattern extending portion in a multi-layer structure, so that the resistance of the folded portion is almost equal to that of the connecting portion. There is an effect that the reference resistance can be set from the pattern width of the portion.
第１図（ａ）は本発明の一実施例の平面図、第１図
（ｂ）は第１図（ａ）の一部の断面図である。 ２……エンコーダ部,3……比較器,4……配線パターン
（基準抵抗用）,5……配線パターン延長部,5A……第１
層目延長部,5b……第２層目延長部,6……スルーホール,
7……配線パターン接続部,9……絶縁層。FIG. 1 (a) is a plan view of an embodiment of the present invention, and FIG. 1 (b) is a partial sectional view of FIG. 1 (a). 2 …… Encoder part, 3 …… comparator, 4 …… wiring pattern (for reference resistance), 5 …… wiring pattern extension, 5A …… first
Layer extension, 5b …… Second layer extension, 6 …… Through hole,
7 …… Wiring pattern connection part, 9 …… Insulation layer.
Claims (1)
折り返し部を介して第２の方向に直線状に延在された配
線パターンを基準抵抗として用いる並列比較型AD変換器
を具備する半導体集積装置において、前記折り返し部は
前記配線パターンと同一幅で、かつ複数並列に配列され
て実質的に基準抵抗として機能する配線パターン接続部
を有し、該配線パターン接続部はその両端部で前記直線
状に延在された配線パターンと接合され、当該接合部は
多層配線構造により低抵抗化され、その上層配線と下層
配線とは前記所定の幅より広く、概略前記配線パターン
接続部の幅に開口されたコンタクトホールで接続されて
いることを特徴とする半導体集積装置。1. A parallel comparison type AD converter which uses a wiring pattern linearly extending in a first direction with a predetermined width and linearly extending in a second direction through a folded portion as a reference resistance. In the semiconductor integrated device, the folded portion has a wiring pattern connecting portion which has the same width as the wiring pattern and is arranged in parallel and substantially functions as a reference resistance. Both ends are joined to the linearly extending wiring pattern, and the joining portion has a low resistance due to a multilayer wiring structure, and the upper layer wiring and the lower layer wiring are wider than the predetermined width, and the wiring pattern connection is substantially the same. A semiconductor integrated device characterized by being connected by a contact hole opened to the width of the portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61132530A JPH0760823B2 (en) | 1986-06-06 | 1986-06-06 | Semiconductor integrated device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61132530A JPH0760823B2 (en) | 1986-06-06 | 1986-06-06 | Semiconductor integrated device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62287644A JPS62287644A (en) | 1987-12-14 |
| JPH0760823B2 true JPH0760823B2 (en) | 1995-06-28 |
Family
ID=15083438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61132530A Expired - Lifetime JPH0760823B2 (en) | 1986-06-06 | 1986-06-06 | Semiconductor integrated device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0760823B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0828662B2 (en) * | 1988-05-10 | 1996-03-21 | 三菱電機株式会社 | A / D converter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS577955A (en) * | 1980-06-17 | 1982-01-16 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| JPS5756959A (en) * | 1980-09-22 | 1982-04-05 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1986
- 1986-06-06 JP JP61132530A patent/JPH0760823B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62287644A (en) | 1987-12-14 |
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